radv: introduce radv_subpass_attachment data structure

[android-x86/external-mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1ea023a..d771c1c 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -446,7 +446,6 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
        MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 
        ++cmd_buffer->state.trace_id;
-       radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
        radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
        radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
@@ -509,7 +508,6 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
        data[0] = (uintptr_t)pipeline;
        data[1] = (uintptr_t)pipeline >> 32;
 
-       radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
        radv_emit_write_data_packet(cs, va, 2, data);
 }
 
@@ -551,7 +549,6 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
                data[i * 2 + 1] = (uintptr_t)set >> 32;
        }
 
-       radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
        radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 }
 
@@ -593,16 +590,9 @@ radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
        uint32_t sh_base = pipeline->user_data_0[stage];
        struct radv_userdata_locations *locs =
                &pipeline->shaders[stage]->info.user_sgprs_locs;
-       unsigned mask;
+       unsigned mask = locs->descriptor_sets_enabled;
 
-       mask = descriptors_state->dirty & descriptors_state->valid;
-
-       for (int i = 0; i < MAX_SETS; i++) {
-               struct radv_userdata_info *loc = &locs->descriptor_sets[i];
-               if (loc->sgpr_idx != -1 && !loc->indirect)
-                       continue;
-               mask &= ~(1 << i);
-       }
+       mask &= descriptors_state->dirty & descriptors_state->valid;
 
        while (mask) {
                int start, count;
@@ -2054,7 +2044,7 @@ static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struc
 }
 
 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
-                                                VkAttachmentReference att)
+                                                struct radv_subpass_attachment att)
 {
        unsigned idx = att.attachment;
        struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
@@ -2313,8 +2303,14 @@ VkResult radv_BeginCommandBuffer(
                radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
        }
 
-       if (unlikely(cmd_buffer->device->trace_bo))
+       if (unlikely(cmd_buffer->device->trace_bo)) {
+               struct radv_device *device = cmd_buffer->device;
+
+               radv_cs_add_buffer(device->ws, cmd_buffer->cs,
+                                  device->trace_bo, 8);
+
                radv_cmd_buffer_trace_emit(cmd_buffer);
+       }
 
        cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
 
@@ -2600,6 +2596,11 @@ VkResult radv_EndCommandBuffer(
                si_emit_cache_flush(cmd_buffer);
        }
 
+       /* Make sure CP DMA is idle at the end of IBs because the kernel
+        * doesn't wait for it.
+        */
+       si_cp_dma_wait_for_idle(cmd_buffer);
+
        vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
 
        if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
@@ -3944,7 +3945,7 @@ void radv_CmdEndRenderPass(
        for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
                VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
                radv_handle_subpass_image_transition(cmd_buffer,
-                                     (VkAttachmentReference){i, layout});
+                                     (struct radv_subpass_attachment){i, layout});
        }
 
        vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
@@ -4246,6 +4247,11 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
                                             0);
        }
 
+       /* Make sure CP DMA is idle because the driver might have performed a
+        * DMA operation for copying or filling buffers/images.
+        */
+       si_cp_dma_wait_for_idle(cmd_buffer);
+
        cmd_buffer->state.flush_bits |= dst_flush_bits;
 }
 
@@ -4296,6 +4302,11 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
                VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
                VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
 
+       /* Make sure CP DMA is idle because the driver might have performed a
+        * DMA operation for copying or filling buffers/images.
+        */
+       si_cp_dma_wait_for_idle(cmd_buffer);
+
        /* TODO: Emit EOS events for syncing PS/CS stages. */
 
        if (!(stageMask & ~top_of_pipe_flags)) {