radv: use separate bind points for the dynamic buffers

[android-x86/external-mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c77a8b2..df335b4 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -833,6 +833,9 @@ enum radv_cmd_flush_bits {
        RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
        RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
        RADV_CMD_FLAG_VGT_FLUSH        = 1 << 12,
+       /* Pipeline query controls. */
+       RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
+       RADV_CMD_FLAG_STOP_PIPELINE_STATS  = 1 << 14,
 
        RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
@@ -930,6 +933,7 @@ struct radv_descriptor_state {
        uint32_t valid;
        struct radv_push_descriptor_set push_set;
        bool push_dirty;
+       uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
 };
 
 struct radv_cmd_state {
@@ -966,6 +970,7 @@ struct radv_cmd_state {
        enum radv_cmd_flush_bits                     flush_bits;
        unsigned                                     active_occlusion_queries;
        bool                                         perfect_occlusion_queries_enabled;
+       unsigned                                     active_pipeline_queries;
        float                                        offset_scale;
        uint32_t                                      trace_id;
        uint32_t                                      last_ia_multi_vgt_param;
@@ -1015,7 +1020,6 @@ struct radv_cmd_buffer {
        uint32_t queue_family_index;
 
        uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
-       uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
        VkShaderStageFlags push_constant_stages;
        struct radv_descriptor_set meta_push_descriptors;
 
@@ -1061,7 +1065,6 @@ uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
                                   bool instanced_draw, bool indirect_draw,
                                   uint32_t draw_vertex_count);
 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
-                               bool predicated,
                                enum chip_class chip_class,
                                bool is_mec,
                                unsigned event, unsigned event_flags,
@@ -1071,7 +1074,6 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
                                uint32_t new_fence);
 
 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
-                       bool predicated,
                        uint64_t va, uint32_t ref,
                        uint32_t mask);
 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
@@ -1781,6 +1783,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
 
 struct radv_fence {
        struct radeon_winsys_fence *fence;
+       struct wsi_fence *fence_wsi;
        bool submitted;
        bool signalled;