radeonsi: move sample positions constant buffer to RW buffers

[android-x86/external-mesa.git] / src / gallium / drivers / radeonsi / si_state.h

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index c4d6b9d..2b566bf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -30,7 +30,8 @@
 #include "si_pm4.h"
 #include "radeon/r600_pipe_common.h"
 
-#define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
+#define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
+#define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
 #define SI_MAX_ATTRIBS 16
 
 struct si_screen;
@@ -68,6 +69,7 @@ struct si_state_rasterizer {
        bool                    uses_poly_offset;
        bool                    clamp_fragment_color;
        bool                    rasterizer_discard;
+       bool                    scissor_enable;
 };
 
 struct si_dsa_stencil_ref_part {
@@ -144,12 +146,8 @@ struct si_shader_data {
        uint32_t                sh_base[SI_NUM_SHADERS];
 };
 
-/* User sampler views:   0..15
- * Polygon stipple tex:  16
- */
-#define SI_NUM_USER_SAMPLERS            16 /* AKA OpenGL textures units per shader */
-#define SI_POLY_STIPPLE_SAMPLER         SI_NUM_USER_SAMPLERS
-#define SI_NUM_SAMPLERS                 (SI_POLY_STIPPLE_SAMPLER + 1)
+#define SI_NUM_USER_SAMPLERS            32 /* AKA OpenGL textures units per shader */
+#define SI_NUM_SAMPLERS                 SI_NUM_USER_SAMPLERS
 
 /* User constant buffers:   0..15
  * Driver state constants:  16
@@ -160,20 +158,32 @@ struct si_shader_data {
 
 #define SI_NUM_IMAGES                  16
 
-/* Read-write buffer slots.
- *
- * Ring buffers:        0..1
- * Streamout buffers:   2..5
- */
-#define SI_RING_TESS_FACTOR    0 /* for HS (TCS)  */
-#define SI_RING_ESGS           0 /* for ES, GS */
-#define SI_RING_GSVS           1 /* for GS, VS */
-#define SI_RING_GSVS_1         2 /* 1, 2, 3 for GS */
-#define SI_RING_GSVS_2         3
-#define SI_RING_GSVS_3         4
-#define SI_NUM_RING_BUFFERS    5
-#define SI_SO_BUF_OFFSET       SI_NUM_RING_BUFFERS
-#define SI_NUM_RW_BUFFERS      (SI_SO_BUF_OFFSET + 4)
+#define SI_NUM_SHADER_BUFFERS          16
+
+/* Private read-write buffer slots. */
+enum {
+       SI_HS_RING_TESS_FACTOR,
+
+       SI_ES_RING_ESGS,
+       SI_GS_RING_ESGS,
+
+       SI_GS_RING_GSVS0,
+       SI_GS_RING_GSVS1,
+       SI_GS_RING_GSVS2,
+       SI_GS_RING_GSVS3,
+       SI_VS_RING_GSVS,
+
+       SI_VS_STREAMOUT_BUF0,
+       SI_VS_STREAMOUT_BUF1,
+       SI_VS_STREAMOUT_BUF2,
+       SI_VS_STREAMOUT_BUF3,
+
+       SI_VS_CONST_CLIP_PLANES,
+       SI_PS_CONST_POLY_STIPPLE,
+       SI_PS_CONST_SAMPLE_POSITIONS,
+
+       SI_NUM_RW_BUFFERS,
+};
 
 #define SI_NUM_VERTEX_BUFFERS  SI_MAX_ATTRIBS
 
@@ -188,16 +198,24 @@ struct si_descriptors {
        unsigned element_dw_size;
        /* The maximum number of descriptors. */
        unsigned num_elements;
-       /* Whether the list has been changed and should be re-uploaded. */
-       bool list_dirty;
 
        /* The buffer where the descriptors have been uploaded. */
        struct r600_resource *buffer;
        unsigned buffer_offset;
 
+       /* Offset in CE RAM */
+       unsigned ce_offset;
+
        /* The i-th bit is set if that element is enabled (non-NULL resource). */
        uint64_t enabled_mask;
 
+       /* elements of the list that are changed and need to be uploaded */
+       uint64_t dirty_mask;
+
+       /* Whether the CE ram is dirty and needs to be reinitialized entirely
+        * before we can do partial updates. */
+       bool ce_ram_dirty;
+
        /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
         * array will be stored. */
        unsigned shader_userdata_offset;
@@ -239,20 +257,27 @@ struct si_buffer_resources {
        } while(0)
 
 /* si_descriptors.c */
+void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
                        struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,
                        unsigned element_size, unsigned index_stride, uint64_t offset);
 void si_init_all_descriptors(struct si_context *sctx);
-bool si_upload_shader_descriptors(struct si_context *sctx);
+bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
+bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 void si_release_all_descriptors(struct si_context *sctx);
 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
                            const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 void si_shader_change_notify(struct si_context *sctx);
 void si_update_compressed_colortex_masks(struct si_context *sctx);
-void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom);
+void si_emit_graphics_shader_userdata(struct si_context *sctx,
+                                      struct r600_atom *atom);
+void si_emit_compute_shader_userdata(struct si_context *sctx);
+void si_set_constant_buffer(struct si_context *sctx,
+                           struct si_buffer_resources *buffers,
+                           uint slot, struct pipe_constant_buffer *input);
 
 /* si_state.c */
 struct si_shader_selector;
@@ -306,6 +331,8 @@ void si_destroy_shader_cache(struct si_screen *sscreen);
 
 /* si_state_draw.c */
 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
+void si_ce_pre_draw_synchronization(struct si_context *sctx);
+void si_ce_post_draw_synchronization(struct si_context *sctx);
 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 void si_trace_emit(struct si_context *sctx);