#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
-#define MFC_SOFTWARE_HASWELL 1
+#define MFC_SOFTWARE_BATCH 0
#define B0_STEP_REV 2
#define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
MFX_HUFFTABLE_ID_UV
};
-static const uint32_t gen8_mfc_batchbuffer_avc_intra[][4] = {
-#include "shaders/utils/mfc_batchbuffer_avc_intra.g7b"
+static const uint32_t gen8_mfc_batchbuffer_avc[][4] = {
+#include "shaders/utils/mfc_batchbuffer_hsw.g8b"
};
-static const uint32_t gen8_mfc_batchbuffer_avc_inter[][4] = {
-#include "shaders/utils/mfc_batchbuffer_avc_inter.g7b"
+static const uint32_t gen9_mfc_batchbuffer_avc[][4] = {
+#include "shaders/utils/mfc_batchbuffer_hsw.g9b"
};
static struct i965_kernel gen8_mfc_kernels[] = {
{
"MFC AVC INTRA BATCHBUFFER ",
MFC_BATCHBUFFER_AVC_INTRA,
- gen8_mfc_batchbuffer_avc_intra,
- sizeof(gen8_mfc_batchbuffer_avc_intra),
+ gen8_mfc_batchbuffer_avc,
+ sizeof(gen8_mfc_batchbuffer_avc),
NULL
},
+};
+static struct i965_kernel gen9_mfc_kernels[] = {
{
- "MFC AVC INTER BATCHBUFFER ",
- MFC_BATCHBUFFER_AVC_INTER,
- gen8_mfc_batchbuffer_avc_inter,
- sizeof(gen8_mfc_batchbuffer_avc_inter),
+ "MFC AVC INTRA BATCHBUFFER ",
+ MFC_BATCHBUFFER_AVC_INTRA,
+ gen9_mfc_batchbuffer_avc,
+ sizeof(gen9_mfc_batchbuffer_avc),
NULL
},
};
+static const uint32_t qm_flat[16] = {
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010
+};
+
+static const uint32_t fqm_flat[32] = {
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000
+};
+
#define INTER_MODE_MASK 0x03
#define INTER_8X8 0x03
#define INTER_16X8 0x01
static void
gen8_mfc_qm_state(VADriverContextP ctx,
int qm_type,
- unsigned int *qm,
+ const uint32_t *qm,
int qm_length,
struct intel_encoder_context *encoder_context)
{
}
static void
-gen8_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+gen8_mfc_avc_qm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
{
- unsigned int qm[16] = {
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010
- };
+ const unsigned int *qm_4x4_intra;
+ const unsigned int *qm_4x4_inter;
+ const unsigned int *qm_8x8_intra;
+ const unsigned int *qm_8x8_inter;
+ VAEncSequenceParameterBufferH264 *pSeqParameter =
+ (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ VAEncPictureParameterBufferH264 *pPicParameter =
+ (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+
+ if (!pSeqParameter->seq_fields.bits.seq_scaling_matrix_present_flag
+ && !pPicParameter->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
+ } else {
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix && encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+ qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
+ qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
+ qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
+ qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
+ }
- gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
- gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
- gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
- gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
+ gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
+ gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
+ gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
+ gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
}
static void
gen8_mfc_fqm_state(VADriverContextP ctx,
int fqm_type,
- unsigned int *fqm,
+ const uint32_t *fqm,
int fqm_length,
struct intel_encoder_context *encoder_context)
{
}
static void
-gen8_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+gen8_mfc_avc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
{
- unsigned int qm[32] = {
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000
- };
+ int i, j;
+ for (i = 0; i < len; i++)
+ for (j = 0; j < len; j++)
+ fqm[i * len + j] = (1 << 16) / qm[j * len + i];
+}
- gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
- gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
- gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
- gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
+static void
+gen8_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAEncSequenceParameterBufferH264 *pSeqParameter =
+ (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ VAEncPictureParameterBufferH264 *pPicParameter =
+ (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+
+ if (!pSeqParameter->seq_fields.bits.seq_scaling_matrix_present_flag
+ && !pPicParameter->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
+ } else {
+ int i;
+ uint32_t fqm[32];
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix && encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+
+ for (i = 0; i < 3; i++)
+ gen8_mfc_avc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
+
+ for (i = 3; i < 6; i++)
+ gen8_mfc_avc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
+
+ gen8_mfc_avc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
+
+ gen8_mfc_avc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
+ gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
+ }
}
static void
mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
- if ( mfc_context->direct_mv_buffers[i].bo != NULL);
- dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
+ if (mfc_context->direct_mv_buffers[i].bo != NULL)
+ dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
mfc_context->direct_mv_buffers[i].bo = NULL;
}
mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
mfc_context->aux_batchbuffer_surface.size_block = 16;
- i965_gpe_context_init(ctx, &mfc_context->gpe_context);
+ gen8_gpe_context_init(ctx, &mfc_context->gpe_context);
}
static void
gen8_mfc_pipe_buf_addr_state(ctx, encoder_context);
gen8_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
mfc_context->avc_img_state(ctx, encode_state, encoder_context);
- mfc_context->avc_qm_state(ctx, encoder_context);
- mfc_context->avc_fqm_state(ctx, encoder_context);
+ mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
+ mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
gen8_mfc_avc_directmode_state(ctx, encoder_context);
intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
}
ADVANCE_BCS_BATCH(batch);
}
-
-#ifdef MFC_SOFTWARE_HASWELL
+#define AVC_INTRA_RDO_OFFSET 4
+#define AVC_INTER_RDO_OFFSET 10
+#define AVC_INTER_MSG_OFFSET 8
+#define AVC_INTER_MV_OFFSET 48
+#define AVC_RDO_MASK 0xFFFF
static int
gen8_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
return len_in_dwords;
}
-#define AVC_INTRA_RDO_OFFSET 4
-#define AVC_INTER_RDO_OFFSET 10
-#define AVC_INTER_MSG_OFFSET 8
-#define AVC_INTER_MV_OFFSET 48
-#define AVC_RDO_MASK 0xFFFF
-
static void
gen8_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
struct encode_state *encode_state,
int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
int is_intra = slice_type == SLICE_TYPE_I;
int qp_slice;
+ int qp_mb;
qp_slice = qp;
if (rate_control_mode == VA_RC_CBR) {
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+ qp = mfc_context->brc.qp_prime_y[0][slice_type];
if (encode_state->slice_header_index[slice_index] == 0) {
pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
qp_slice = qp;
x = i % width_in_mbs;
y = i / width_in_mbs;
msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
+ if (vme_context->roi_enabled) {
+ qp_mb = *(vme_context->qp_per_mb + i);
+ } else
+ qp_mb = qp;
if (is_intra) {
assert(msg);
- gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
+ gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
} else {
int inter_rdo, intra_rdo;
inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK;
intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK;
offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET;
if (intra_rdo < inter_rdo) {
- gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
+ gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
} else {
msg += AVC_INTER_MSG_OFFSET;
- gen8_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
+ gen8_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
}
}
}
struct intel_encoder_context *encoder_context)
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch;
dri_bo *batch_bo;
int i;
return batch_bo;
}
-#else
static void
gen8_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
struct encode_state *encode_state,
struct intel_encoder_context *encoder_context)
-
{
struct gen6_vme_context *vme_context = encoder_context->vme_context;
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
&vme_context->vme_output,
BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
- assert(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->buffer_suface_setup(ctx,
- &mfc_context->gpe_context,
- &mfc_context->aux_batchbuffer_surface,
- BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
- SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
}
static void
gen8_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
struct encode_state *encode_state,
struct intel_encoder_context *encoder_context)
-
{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
- mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
- mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
- mfc_context->mfc_batchbuffer_surface.pitch = 16;
- mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
- "MFC batchbuffer",
- mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
- 0x1000);
+ assert(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->buffer_suface_setup(ctx,
&mfc_context->gpe_context,
- &mfc_context->mfc_batchbuffer_surface,
+ &mfc_context->aux_batchbuffer_surface,
BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
}
struct intel_encoder_context *encoder_context)
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_interface_descriptor_data *desc;
+ struct gen8_interface_descriptor_data *desc;
int i;
dri_bo *bo;
+ unsigned char *desc_ptr;
- bo = mfc_context->gpe_context.idrt.bo;
+ bo = mfc_context->gpe_context.dynamic_state.bo;
dri_bo_map(bo, 1);
assert(bo->virtual);
- desc = bo->virtual;
+ desc_ptr = (unsigned char *)bo->virtual + mfc_context->gpe_context.idrt_offset;
+
+ desc = (struct gen8_interface_descriptor_data *)desc_ptr;
for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
struct i965_kernel *kernel;
-
kernel = &mfc_context->gpe_context.kernels[i];
assert(sizeof(*desc) == 32);
-
/*Setup the descritor table*/
memset(desc, 0, sizeof(*desc));
- desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
- desc->desc2.sampler_count = 0;
- desc->desc2.sampler_state_pointer = 0;
- desc->desc3.binding_table_entry_count = 2;
- desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
- desc->desc4.constant_urb_entry_read_offset = 0;
- desc->desc4.constant_urb_entry_read_length = 4;
+ desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6;
+ desc->desc3.sampler_count = 0;
+ desc->desc3.sampler_state_pointer = 0;
+ desc->desc4.binding_table_entry_count = 1;
+ desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
+ desc->desc5.constant_urb_entry_read_offset = 0;
+ desc->desc5.constant_urb_entry_read_length = 4;
+
- /*kernel start*/
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0,
- i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
- kernel->bo);
desc++;
}
dri_bo_unmap(bo);
+
+ return;
}
static void
(void)mfc_context;
}
+#define AVC_PAK_LEN_IN_BYTE 48
+#define AVC_PAK_LEN_IN_OWORD 3
+
static void
gen8_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
- int index,
- int head_offset,
- int batchbuffer_offset,
- int head_size,
- int tail_size,
- int number_mb_cmds,
- int first_object,
- int last_object,
- int last_slice,
- int mb_x,
- int mb_y,
- int width_in_mbs,
- int qp)
+ uint32_t intra_flag,
+ int head_offset,
+ int number_mb_cmds,
+ int slice_end_x,
+ int slice_end_y,
+ int mb_x,
+ int mb_y,
+ int width_in_mbs,
+ int qp,
+ uint32_t fwd_ref,
+ uint32_t bwd_ref)
{
- BEGIN_BATCH(batch, 12);
+ uint32_t temp_value;
+ BEGIN_BATCH(batch, 14);
- OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
- OUT_BATCH(batch, index);
+ OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
+ OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
/*inline data */
- OUT_BATCH(batch, head_offset);
- OUT_BATCH(batch, batchbuffer_offset);
- OUT_BATCH(batch,
- head_size << 16 |
- tail_size);
- OUT_BATCH(batch,
- number_mb_cmds << 16 |
- first_object << 2 |
- last_object << 1 |
- last_slice);
- OUT_BATCH(batch,
- mb_y << 8 |
- mb_x);
+ OUT_BATCH(batch, head_offset / 16);
+ OUT_BATCH(batch, (intra_flag) | (qp << 16));
+ temp_value = (mb_x | (mb_y << 8) | (width_in_mbs << 16));
+ OUT_BATCH(batch, temp_value);
+
+ OUT_BATCH(batch, number_mb_cmds);
+
OUT_BATCH(batch,
- qp << 16 |
- width_in_mbs);
+ ((slice_end_y << 8) | (slice_end_x)));
+ OUT_BATCH(batch, fwd_ref);
+ OUT_BATCH(batch, bwd_ref);
+
+ OUT_BATCH(batch, MI_NOOP);
ADVANCE_BATCH(batch);
}
static void
gen8_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context,
- VAEncSliceParameterBufferH264 *slice_param,
- int head_offset,
- unsigned short head_size,
- unsigned short tail_size,
- int batchbuffer_offset,
- int qp,
- int last_slice)
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ int head_offset,
+ int qp,
+ int last_slice)
{
struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct gen6_vme_context *vme_context = encoder_context->vme_context;
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
int total_mbs = slice_param->num_macroblocks;
+ int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
int number_mb_cmds = 128;
- int starting_mb = 0;
- int last_object = 0;
- int first_object = 1;
- int i;
+ int starting_offset = 0;
int mb_x, mb_y;
- int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
+ int last_mb, slice_end_x, slice_end_y;
+ int remaining_mb = total_mbs;
+ uint32_t fwd_ref , bwd_ref, mb_flag;
+ char tmp_qp;
+ int number_roi_mbs, max_mb_cmds, i;
+
+ last_mb = slice_param->macroblock_address + total_mbs - 1;
+ slice_end_x = last_mb % width_in_mbs;
+ slice_end_y = last_mb / width_in_mbs;
- for (i = 0; i < total_mbs / number_mb_cmds; i++) {
- last_object = (total_mbs - starting_mb) == number_mb_cmds;
- mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
- mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
- assert(mb_x <= 255 && mb_y <= 255);
+ if (slice_type == SLICE_TYPE_I) {
+ fwd_ref = 0;
+ bwd_ref = 0;
+ mb_flag = 1;
+ } else {
+ fwd_ref = vme_context->ref_index_in_mb[0];
+ bwd_ref = vme_context->ref_index_in_mb[1];
+ mb_flag = 0;
+ }
- starting_mb += number_mb_cmds;
+ if (width_in_mbs >= 100) {
+ number_mb_cmds = width_in_mbs / 5;
+ } else if (width_in_mbs >= 80) {
+ number_mb_cmds = width_in_mbs / 4;
+ } else if (width_in_mbs >= 60) {
+ number_mb_cmds = width_in_mbs / 3;
+ } else if (width_in_mbs >= 40) {
+ number_mb_cmds = width_in_mbs / 2;
+ } else {
+ number_mb_cmds = width_in_mbs;
+ }
- gen8_mfc_batchbuffer_emit_object_command(batch,
- index,
- head_offset,
- batchbuffer_offset,
- head_size,
- tail_size,
- number_mb_cmds,
- first_object,
- last_object,
- last_slice,
- mb_x,
- mb_y,
- width_in_mbs,
- qp);
-
- if (first_object) {
- head_offset += head_size;
- batchbuffer_offset += head_size;
- }
+ max_mb_cmds = number_mb_cmds;
- if (last_object) {
- head_offset += tail_size;
- batchbuffer_offset += tail_size;
- }
+ do {
+ mb_x = (slice_param->macroblock_address + starting_offset) % width_in_mbs;
+ mb_y = (slice_param->macroblock_address + starting_offset) / width_in_mbs;
- batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
+ number_mb_cmds = max_mb_cmds;
+ if (vme_context->roi_enabled) {
- first_object = 0;
- }
+ number_roi_mbs = 1;
+ tmp_qp = *(vme_context->qp_per_mb + starting_offset);
+ for (i = 1; i < max_mb_cmds; i++) {
+ if (tmp_qp != *(vme_context->qp_per_mb + starting_offset + i))
+ break;
- if (!last_object) {
- last_object = 1;
- number_mb_cmds = total_mbs % number_mb_cmds;
- mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
- mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
- assert(mb_x <= 255 && mb_y <= 255);
- starting_mb += number_mb_cmds;
+ number_roi_mbs++;
+ }
+
+ number_mb_cmds = number_roi_mbs;
+ qp = tmp_qp;
+ }
+
+ if (number_mb_cmds >= remaining_mb) {
+ number_mb_cmds = remaining_mb;
+ }
gen8_mfc_batchbuffer_emit_object_command(batch,
- index,
- head_offset,
- batchbuffer_offset,
- head_size,
- tail_size,
- number_mb_cmds,
- first_object,
- last_object,
- last_slice,
- mb_x,
- mb_y,
- width_in_mbs,
- qp);
- }
+ mb_flag,
+ head_offset,
+ number_mb_cmds,
+ slice_end_x,
+ slice_end_y,
+ mb_x,
+ mb_y,
+ width_in_mbs,
+ qp,
+ fwd_ref,
+ bwd_ref);
+
+ head_offset += (number_mb_cmds * AVC_PAK_LEN_IN_BYTE);
+ remaining_mb -= number_mb_cmds;
+ starting_offset += number_mb_cmds;
+ } while (remaining_mb > 0);
}
-
-/*
- * return size in Owords (16bytes)
- */
-static int
+
+static void
gen8_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index,
- int batchbuffer_offset)
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int slice_index)
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
unsigned int rate_control_mode = encoder_context->rate_control_mode;
unsigned int tail_data[] = { 0x0, 0x0 };
long head_offset;
- int old_used = intel_batchbuffer_used_size(slice_batch), used;
- unsigned short head_size, tail_size;
int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
int qp_slice;
qp_slice = qp;
if (rate_control_mode == VA_RC_CBR) {
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+ qp = mfc_context->brc.qp_prime_y[0][slice_type];
if (encode_state->slice_header_index[slice_index] == 0) {
pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
qp_slice = qp;
assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
assert(qp >= 0 && qp < 52);
- head_offset = old_used / 16;
gen8_mfc_avc_slice_state(ctx,
- pPicParameter,
- pSliceParameter,
- encode_state,
- encoder_context,
- (rate_control_mode == VA_RC_CBR),
- qp_slice,
- slice_batch);
+ pPicParameter,
+ pSliceParameter,
+ encode_state,
+ encoder_context,
+ (rate_control_mode == VA_RC_CBR),
+ qp_slice,
+ slice_batch);
if (slice_index == 0)
intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
- used = intel_batchbuffer_used_size(slice_batch);
- head_size = (used - old_used) / 16;
- old_used = used;
+ head_offset = intel_batchbuffer_used_size(slice_batch);
- /* tail */
+ slice_batch->ptr += pSliceParameter->num_macroblocks * AVC_PAK_LEN_IN_BYTE;
+
+ gen8_mfc_avc_batchbuffer_slice_command(ctx,
+ encoder_context,
+ pSliceParameter,
+ head_offset,
+ qp,
+ last_slice);
+
+
+ /* Aligned for tail */
+ intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
if (last_slice) {
mfc_context->insert_object(ctx,
encoder_context,
slice_batch);
}
- intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
- used = intel_batchbuffer_used_size(slice_batch);
- tail_size = (used - old_used) / 16;
-
-
- gen8_mfc_avc_batchbuffer_slice_command(ctx,
- encoder_context,
- pSliceParameter,
- head_offset,
- head_size,
- tail_size,
- batchbuffer_offset,
- qp,
- last_slice);
-
- return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
+ return;
}
static void
struct encode_state *encode_state,
struct intel_encoder_context *encoder_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
struct intel_batchbuffer *batch = encoder_context->base.batch;
- int i, size, offset = 0;
- intel_batchbuffer_start_atomic(batch, 0x4000);
- gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
+ int i;
+
+ intel_batchbuffer_start_atomic(batch, 0x4000);
+
+ if (IS_GEN9(i965->intel.device_info))
+ gen9_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
+ else
+ gen8_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
- size = gen8_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
- offset += size;
+ gen8_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i);
+ }
+ {
+ struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
+
+ intel_batchbuffer_align(slice_batch, 8);
+ BEGIN_BCS_BATCH(slice_batch, 2);
+ OUT_BCS_BATCH(slice_batch, 0);
+ OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
+ ADVANCE_BCS_BATCH(slice_batch);
+
+ BEGIN_BATCH(batch, 2);
+ OUT_BATCH(batch, CMD_MEDIA_STATE_FLUSH);
+ OUT_BATCH(batch, 0);
+ ADVANCE_BATCH(batch);
}
intel_batchbuffer_end_atomic(batch);
intel_batchbuffer_flush(batch);
+
+ if (IS_GEN9(i965->intel.device_info))
+ gen9_gpe_pipeline_end(ctx, &mfc_context->gpe_context, batch);
}
static void
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
+ dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
gen8_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
- dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
- return mfc_context->mfc_batchbuffer_surface.bo;
+ return mfc_context->aux_batchbuffer_surface.bo;
}
-#endif
-
static void
gen8_mfc_avc_pipeline_programing(VADriverContextP ctx,
struct encode_state *encode_state,
return;
}
-#ifdef MFC_SOFTWARE_HASWELL
- slice_batch_bo = gen8_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
-#else
- slice_batch_bo = gen8_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
-#endif
+ if (encoder_context->soft_batch_force)
+ slice_batch_bo = gen8_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
+ else
+ slice_batch_bo = gen8_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
+
// begin programing
intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
gen8_mfc_run(ctx, encode_state, encoder_context);
if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
gen8_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
- sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
+ sts = intel_mfc_brc_postpack(encode_state, encoder_context, current_frame_bits_size);
if (sts == BRC_NO_HRD_VIOLATION) {
intel_mfc_hrd_context_update(encode_state, mfc_context);
break;
struct intel_encoder_context *encoder_context)
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch;
VAEncSliceParameterBufferMPEG2 *next_slice_group_param = NULL;
dri_bo *batch_bo;
uint8_t huff_si_table[huff_val_size];
uint16_t huff_co_table[huff_val_size];
- memset(huff_si_table, 0, huff_val_size);
- memset(huff_co_table, 0, huff_val_size);
+ memset(huff_si_table, 0, sizeof(huff_si_table));
+ memset(huff_co_table, 0, sizeof(huff_co_table));
do {
i = map_huffval_to_index(huff_vals[k]);
//I dont think I need this for loop. Just to be consistent with other encoding logic...
for(i = 0; i < encode_state->num_slice_params_ext; i++) {
- assert(encode_state->slice_params && encode_state->slice_params_ext[i]->buffer);
+ assert(encode_state->slice_params_ext && encode_state->slice_params_ext[i]->buffer);
slice_param = (VAEncSliceParameterBufferJPEG *)encode_state->slice_params_ext[i]->buffer;
for(j = 0; j < encode_state->slice_params_ext[i]->num_elements; j++) {
return target_qindex;
}
-static void
-gen8_mfc_vp8_bit_rate_control_context_init(struct encode_state *encode_state,
- struct gen6_mfc_context *mfc_context)
-{
- VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
- VAEncMiscParameterBuffer *misc_param_frame_rate_buffer = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeFrameRate]->buffer;
- VAEncMiscParameterFrameRate* param_frame_rate = (VAEncMiscParameterFrameRate*)misc_param_frame_rate_buffer->data;
- int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
- int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
- float fps = param_frame_rate->framerate;
- int inter_mb_size = seq_param->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs;
- int intra_mb_size = inter_mb_size * 5.0;
-
- mfc_context->bit_rate_control_context[SLICE_TYPE_I].target_mb_size = intra_mb_size;
- mfc_context->bit_rate_control_context[SLICE_TYPE_I].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs;
- mfc_context->bit_rate_control_context[SLICE_TYPE_P].target_mb_size = inter_mb_size;
- mfc_context->bit_rate_control_context[SLICE_TYPE_P].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs;
-
- mfc_context->bit_rate_control_context[SLICE_TYPE_I].TargetSizeInWord = (intra_mb_size + 16)/ 16;
- mfc_context->bit_rate_control_context[SLICE_TYPE_P].TargetSizeInWord = (inter_mb_size + 16)/ 16;
-
- mfc_context->bit_rate_control_context[SLICE_TYPE_I].MaxSizeInWord = mfc_context->bit_rate_control_context[SLICE_TYPE_I].TargetSizeInWord * 1.5;
- mfc_context->bit_rate_control_context[SLICE_TYPE_P].MaxSizeInWord = mfc_context->bit_rate_control_context[SLICE_TYPE_P].TargetSizeInWord * 1.5;
-}
-
static void gen8_mfc_vp8_brc_init(struct encode_state *encode_state,
struct intel_encoder_context* encoder_context)
{
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
- VAEncMiscParameterBuffer* misc_param_hrd = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeHRD]->buffer;
+ VAEncMiscParameterBuffer* misc_param_hrd = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeHRD][0]->buffer;
VAEncMiscParameterHRD* param_hrd = (VAEncMiscParameterHRD*)misc_param_hrd->data;
- VAEncMiscParameterBuffer* misc_param_frame_rate_buffer = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeFrameRate]->buffer;
+ VAEncMiscParameterBuffer* misc_param_frame_rate_buffer = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeFrameRate][0]->buffer;
VAEncMiscParameterFrameRate* param_frame_rate = (VAEncMiscParameterFrameRate*)misc_param_frame_rate_buffer->data;
double bitrate = seq_param->bits_per_second;
unsigned int frame_rate = param_frame_rate->framerate;
mfc_context->brc.mode = encoder_context->rate_control_mode;
- mfc_context->brc.target_frame_size[SLICE_TYPE_I] = (int)((double)((bitrate * intra_period)/frame_rate) /
+ mfc_context->brc.target_frame_size[0][SLICE_TYPE_I] = (int)((double)((bitrate * intra_period)/frame_rate) /
(double)(inum + BRC_PWEIGHT * pnum ));
- mfc_context->brc.target_frame_size[SLICE_TYPE_P] = BRC_PWEIGHT * mfc_context->brc.target_frame_size[SLICE_TYPE_I];
+ mfc_context->brc.target_frame_size[0][SLICE_TYPE_P] = BRC_PWEIGHT * mfc_context->brc.target_frame_size[0][SLICE_TYPE_I];
mfc_context->brc.gop_nums[SLICE_TYPE_I] = inum;
mfc_context->brc.gop_nums[SLICE_TYPE_P] = pnum;
- mfc_context->brc.bits_per_frame = bitrate/frame_rate;
+ mfc_context->brc.bits_per_frame[0] = bitrate/frame_rate;
- mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY = gen8_mfc_vp8_qindex_estimate(encode_state,
- mfc_context,
- mfc_context->brc.target_frame_size[SLICE_TYPE_I],
- 1);
- mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY = gen8_mfc_vp8_qindex_estimate(encode_state,
- mfc_context,
- mfc_context->brc.target_frame_size[SLICE_TYPE_P],
- 0);
+ mfc_context->brc.qp_prime_y[0][SLICE_TYPE_I] = gen8_mfc_vp8_qindex_estimate(encode_state,
+ mfc_context,
+ mfc_context->brc.target_frame_size[0][SLICE_TYPE_I],
+ 1);
+ mfc_context->brc.qp_prime_y[0][SLICE_TYPE_P] = gen8_mfc_vp8_qindex_estimate(encode_state,
+ mfc_context,
+ mfc_context->brc.target_frame_size[0][SLICE_TYPE_P],
+ 0);
mfc_context->hrd.buffer_size = (double)param_hrd->buffer_size;
mfc_context->hrd.current_buffer_fullness =
}
static int gen8_mfc_vp8_brc_postpack(struct encode_state *encode_state,
- struct gen6_mfc_context *mfc_context,
+ struct intel_encoder_context *encoder_context,
int frame_bits)
{
+ struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
gen6_brc_status sts = BRC_NO_HRD_VIOLATION;
VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
int is_key_frame = !pic_param->pic_flags.bits.frame_type;
int slicetype = (is_key_frame ? SLICE_TYPE_I : SLICE_TYPE_P);
- int qpi = mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY;
- int qpp = mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY;
+ int qpi = mfc_context->brc.qp_prime_y[0][SLICE_TYPE_I];
+ int qpp = mfc_context->brc.qp_prime_y[0][SLICE_TYPE_P];
int qp; // quantizer of previously encoded slice of current type
int qpn; // predicted quantizer for next frame of current type in integer format
double qpf; // predicted quantizer for next frame of current type in float format
unsigned int max_qindex = pic_param->clamp_qindex_high;
unsigned int min_qindex = pic_param->clamp_qindex_low;
- qp = mfc_context->bit_rate_control_context[slicetype].QpPrimeY;
+ qp = mfc_context->brc.qp_prime_y[0][slicetype];
- target_frame_size = mfc_context->brc.target_frame_size[slicetype];
+ target_frame_size = mfc_context->brc.target_frame_size[0][slicetype];
if (mfc_context->hrd.buffer_capacity < 5)
frame_size_alpha = 0;
else
BRC_CLIP(qpn, min_qindex, max_qindex);
/* checking wthether HRD compliance is still met */
- sts = intel_mfc_update_hrd(encode_state, mfc_context, frame_bits);
+ sts = intel_mfc_update_hrd(encode_state, encoder_context, frame_bits);
/* calculating QP delta as some function*/
x = mfc_context->hrd.target_buffer_fullness - mfc_context->hrd.current_buffer_fullness;
/* correcting QPs of slices of other types */
if (!is_key_frame) {
if (abs(qpn - BRC_I_P_QP_DIFF - qpi) > 4)
- mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY += (qpn - BRC_I_P_QP_DIFF - qpi) >> 2;
+ mfc_context->brc.qp_prime_y[0][SLICE_TYPE_I] += (qpn - BRC_I_P_QP_DIFF - qpi) >> 2;
} else {
if (abs(qpn + BRC_I_P_QP_DIFF - qpp) > 4)
- mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY += (qpn + BRC_I_P_QP_DIFF - qpp) >> 2;
+ mfc_context->brc.qp_prime_y[0][SLICE_TYPE_P] += (qpn + BRC_I_P_QP_DIFF - qpp) >> 2;
}
- BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY, min_qindex, max_qindex);
- BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY, min_qindex, max_qindex);
+ BRC_CLIP(mfc_context->brc.qp_prime_y[0][SLICE_TYPE_I], min_qindex, max_qindex);
+ BRC_CLIP(mfc_context->brc.qp_prime_y[0][SLICE_TYPE_P], min_qindex, max_qindex);
} else if (sts == BRC_UNDERFLOW) { // underflow
if (qpn <= qp) qpn = qp + 2;
if (qpn > max_qindex) {
}
}
- mfc_context->bit_rate_control_context[slicetype].QpPrimeY = qpn;
+ mfc_context->brc.qp_prime_y[0][slicetype] = qpn;
return sts;
}
// current we only support CBR mode.
if (rate_control_mode == VA_RC_CBR) {
mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10;
- mfc_context->vui_hrd.i_cpb_size_value = (target_bit_rate * 8) >> 10;
- mfc_context->vui_hrd.i_initial_cpb_removal_delay = mfc_context->vui_hrd.i_cpb_size_value * 0.5 * 1024 / target_bit_rate * 90000;
+ mfc_context->vui_hrd.i_initial_cpb_removal_delay = ((target_bit_rate * 8) >> 10) * 0.5 * 1024 / target_bit_rate * 90000;
mfc_context->vui_hrd.i_cpb_removal_delay = 2;
mfc_context->vui_hrd.i_frame_number = 0;
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
double cur_fps, cur_bitrate;
VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
- VAEncMiscParameterBuffer *misc_param_frame_rate_buf = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeFrameRate]->buffer;
+ VAEncMiscParameterBuffer *misc_param_frame_rate_buf = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeFrameRate][0]->buffer;
VAEncMiscParameterFrameRate *param_frame_rate = (VAEncMiscParameterFrameRate*)misc_param_frame_rate_buf->data;
unsigned int frame_rate = param_frame_rate->framerate;
struct intel_encoder_context *encoder_context)
{
unsigned int rate_control_mode = encoder_context->rate_control_mode;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
if (rate_control_mode == VA_RC_CBR) {
bool brc_updated;
brc_updated = gen8_mfc_vp8_brc_updated_check(encode_state, encoder_context);
/*Programing bit rate control */
- if ((mfc_context->bit_rate_control_context[SLICE_TYPE_I].MaxSizeInWord == 0) ||
- brc_updated) {
- gen8_mfc_vp8_bit_rate_control_context_init(encode_state, mfc_context);
+ if (brc_updated) {
gen8_mfc_vp8_brc_init(encode_state, encoder_context);
}
/*Programing HRD control */
- if ((mfc_context->vui_hrd.i_cpb_size_value == 0) || brc_updated )
+ if (brc_updated)
gen8_mfc_vp8_hrd_context_init(encode_state, encoder_context);
}
}
frame_header_buffer = (unsigned char *)mfc_context->vp8_state.frame_header_bo->virtual;
assert(frame_header_buffer);
memcpy(frame_header_buffer, mfc_context->vp8_state.vp8_frame_header, (mfc_context->vp8_state.frame_header_bit_count + 7) / 8);
+ free(mfc_context->vp8_state.vp8_frame_header);
dri_bo_unmap(mfc_context->vp8_state.frame_header_bo);
}
rate_control_mode = encoder_context->rate_control_mode;
if (rate_control_mode == VA_RC_CBR) {
- q_matrix->quantization_index[0] = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+ q_matrix->quantization_index[0] = mfc_context->brc.qp_prime_y[0][slice_type];
for (i = 1; i < 4; i++)
q_matrix->quantization_index[i] = q_matrix->quantization_index[0];
for (i = 0; i < 5; i++)
dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->aux_batchbuffer_surface.bo = NULL;
- if (mfc_context->aux_batchbuffer)
+ if (mfc_context->aux_batchbuffer) {
intel_batchbuffer_free(mfc_context->aux_batchbuffer);
+ mfc_context->aux_batchbuffer = NULL;
+ }
mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, slice_batchbuffer_size);
mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
mfc_context->aux_batchbuffer_surface.size_block = 16;
- i965_gpe_context_init(ctx, &mfc_context->gpe_context);
+ gen8_gpe_context_init(ctx, &mfc_context->gpe_context);
/* alloc vp8 encoding buffers*/
dri_bo_unreference(mfc_context->vp8_state.frame_header_bo);
struct encode_state *encode_state,
struct intel_encoder_context *encoder_context)
{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
unsigned char is_intra_frame = !pic_param->pic_flags.bits.frame_type;
current_frame_bits_size = 8 * gen8_mfc_calc_vp8_coded_buffer_size(ctx, encode_state, encoder_context);
if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
- sts = gen8_mfc_vp8_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
+ sts = gen8_mfc_vp8_brc_postpack(encode_state, encoder_context, current_frame_bits_size);
if (sts == BRC_NO_HRD_VIOLATION) {
gen8_mfc_vp8_hrd_context_update(encode_state, mfc_context);
}
mfc_context->reference_surfaces[i].bo = NULL;
}
- i965_gpe_context_destroy(&mfc_context->gpe_context);
+ gen8_gpe_context_destroy(&mfc_context->gpe_context);
dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
mfc_context->mfc_batchbuffer_surface.bo = NULL;
Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
+
assert(mfc_context);
mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
- mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
- mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
-
- mfc_context->gpe_context.curbe.length = 32 * 4;
+ mfc_context->gpe_context.idrt_size = sizeof(struct gen8_interface_descriptor_data) * MAX_INTERFACE_DESC_GEN6;
+ mfc_context->gpe_context.curbe_size = 32 * 4;
+ mfc_context->gpe_context.sampler_size = 0;
mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
- i965_gpe_load_kernels(ctx,
+ if (IS_GEN9(i965->intel.device_info)) {
+ gen8_gpe_load_kernels(ctx,
+ &mfc_context->gpe_context,
+ gen9_mfc_kernels,
+ 1);
+ } else {
+ gen8_gpe_load_kernels(ctx,
&mfc_context->gpe_context,
gen8_mfc_kernels,
- NUM_MFC_KERNEL);
+ 1);
+ }
mfc_context->pipe_mode_select = gen8_mfc_pipe_mode_select;
mfc_context->set_surface_state = gen8_mfc_surface_state;
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