Set the pipeline to use the new VP8 encoding shaders on BSW

[android-x86/hardware-intel-common-vaapi.git] / src / gen8_mfd.c

diff --git a/src/gen8_mfd.c b/src/gen8_mfd.c
index 0b39dac..07d0968 100644 (file)
--- a/src/gen8_mfd.c
+++ b/src/gen8_mfd.c
@@ -74,6 +74,11 @@ gen8_mfd_init_avc_surface(VADriverContextP ctx,
 
     if (!gen7_avc_surface) {
         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
+
+        if (!gen7_avc_surface)
+            return;
+
+        gen7_avc_surface->base.frame_store_id = -1;
         assert((obj_surface->size & 0x3f) == 0);
         obj_surface->private_data = gen7_avc_surface;
     }
@@ -174,6 +179,7 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
                              int standard_select,
                              struct gen7_mfd_context *gen7_mfd_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
     int i;
 
@@ -181,24 +187,27 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
        /* Pre-deblock 1-3 */
     if (gen7_mfd_context->pre_deblocking_output.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->pre_deblocking_output.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-    else
+    else {
         OUT_BCS_BATCH(batch, 0);
 
        OUT_BCS_BATCH(batch, 0);
-       OUT_BCS_BATCH(batch, 0);
+    }
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
+
        /* Post-debloing 4-6 */
     if (gen7_mfd_context->post_deblocking_output.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->post_deblocking_output.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-    else
+    else {
         OUT_BCS_BATCH(batch, 0);
 
        OUT_BCS_BATCH(batch, 0);
-       OUT_BCS_BATCH(batch, 0);
+    }
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
        /* uncompressed-video & stream out 7-12 */
     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
@@ -210,23 +219,27 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 
        /* intra row-store scratch 13-15 */
     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-    else
+    else {
         OUT_BCS_BATCH(batch, 0);
 
        OUT_BCS_BATCH(batch, 0);
-       OUT_BCS_BATCH(batch, 0);
+    }
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
+
        /* deblocking-filter-row-store 16-18 */
     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-    else
+    else {
         OUT_BCS_BATCH(batch, 0);
        OUT_BCS_BATCH(batch, 0);
-       OUT_BCS_BATCH(batch, 0);
+    }
+
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
     /* DW 19..50 */
     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
@@ -237,18 +250,18 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
             gen7_mfd_context->reference_surface[i].obj_surface->bo) {
             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 
-            OUT_BCS_RELOC(batch, obj_surface->bo,
+            OUT_BCS_RELOC64(batch, obj_surface->bo,
                           I915_GEM_DOMAIN_INSTRUCTION, 0,
                           0);
         } else {
             OUT_BCS_BATCH(batch, 0);
+            OUT_BCS_BATCH(batch, 0);
         }
         
-        OUT_BCS_BATCH(batch, 0);
     }
     
     /* reference property 51 */
-    OUT_BCS_BATCH(batch, 0);  
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
        
     /* Macroblock status & ILDB 52-57 */
     OUT_BCS_BATCH(batch, 0);
@@ -273,15 +286,15 @@ gen8_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
                                  struct gen7_mfd_context *gen7_mfd_context)
 {
     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
 
     BEGIN_BCS_BATCH(batch, 26);
     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
        /* MFX In BS 1-5 */
-    OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_RELOC64(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
        /* Upper bound 4-5 */   
-    OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
+    OUT_BCS_BATCH(batch, 0);
     OUT_BCS_BATCH(batch, 0);
 
        /* MFX indirect MV 6-10 */
@@ -322,39 +335,43 @@ gen8_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
                                  struct gen7_mfd_context *gen7_mfd_context)
 {
     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
 
     BEGIN_BCS_BATCH(batch, 10);
     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
 
     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-       else
+       else {
                OUT_BCS_BATCH(batch, 0);
+               OUT_BCS_BATCH(batch, 0);
+    }
                
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
        /* MPR Row Store Scratch buffer 4-6 */
     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-    else
+    else {
+        OUT_BCS_BATCH(batch, 0);
         OUT_BCS_BATCH(batch, 0);
+    }
 
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
        /* Bitplane 7-9 */ 
     if (gen7_mfd_context->bitplane_read_buffer.valid)
-        OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->bitplane_read_buffer.bo,
                       I915_GEM_DOMAIN_INSTRUCTION, 0,
                       0);
-    else
+    else {
        OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+       OUT_BCS_BATCH(batch, 0);
+    }
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
     ADVANCE_BCS_BATCH(batch);
 }
 
@@ -505,6 +522,7 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
                               VASliceParameterBufferH264 *slice_param,
                               struct gen7_mfd_context *gen7_mfd_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
     struct object_surface *obj_surface;
     GenAvcSurface *gen7_avc_surface;
@@ -523,17 +541,16 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
             gen7_avc_surface = obj_surface->private_data;
 
-            OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
+            OUT_BCS_RELOC64(batch, gen7_avc_surface->dmv_top,
                           I915_GEM_DOMAIN_INSTRUCTION, 0,
                           0);
-            OUT_BCS_BATCH(batch, 0);
         } else {
             OUT_BCS_BATCH(batch, 0);
             OUT_BCS_BATCH(batch, 0);
         }
     }
     
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
     /* the current decoding frame/field */
     va_pic = &pic_param->CurrPic;
@@ -541,12 +558,11 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
     assert(obj_surface->bo && obj_surface->private_data);
     gen7_avc_surface = obj_surface->private_data;
 
-    OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
+    OUT_BCS_RELOC64(batch, gen7_avc_surface->dmv_top,
                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                   0);
 
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
     /* POC List */
     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
@@ -574,6 +590,15 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
 }
 
 static void
+gen8_mfd_avc_phantom_slice_first(VADriverContextP ctx,
+                                 VAPictureParameterBufferH264 *pic_param,
+                                 VASliceParameterBufferH264 *next_slice_param,
+                                 struct gen7_mfd_context *gen7_mfd_context)
+{
+    gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
+}
+
+static void
 gen8_mfd_avc_slice_state(VADriverContextP ctx,
                          VAPictureParameterBufferH264 *pic_param,
                          VASliceParameterBufferH264 *slice_param,
@@ -615,14 +640,19 @@ gen8_mfd_avc_slice_state(VADriverContextP ctx,
         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
     }
 
-    first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
+    first_mb_in_slice = slice_param->first_mb_in_slice;
     slice_hor_pos = first_mb_in_slice % width_in_mbs; 
     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 
+    if (mbaff_picture)
+        slice_ver_pos = slice_ver_pos << 1;
     if (next_slice_param) {
-        first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
+        first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; 
         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
+
+        if (mbaff_picture)
+            next_slice_ver_pos = next_slice_ver_pos << 1;
     } else {
         next_slice_hor_pos = 0;
         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
@@ -814,8 +844,10 @@ gen8_mfd_avc_decode_init(VADriverContextP ctx,
 
     /* Current decoded picture */
     obj_surface = decode_state->render_object;
-    obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
-    obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
+    if (pic_param->pic_fields.bits.reference_pic_flag)
+        obj_surface->flags |= SURFACE_REFERENCED;
+    else
+        obj_surface->flags &= ~SURFACE_REFERENCED;
 
     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
     gen8_mfd_init_avc_surface(ctx, pic_param, obj_surface);
@@ -905,6 +937,9 @@ gen8_mfd_avc_decode_picture(VADriverContextP ctx,
         else
             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 
+        if (j == 0 && slice_param->first_mb_in_slice)
+            gen8_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context); 
+
         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
             assert((slice_param->slice_type == SLICE_TYPE_I) ||
@@ -1253,6 +1288,10 @@ gen8_mfd_init_vc1_surface(VADriverContextP ctx,
 
     if (!gen7_vc1_surface) {
         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
+
+        if (!gen7_vc1_surface)
+            return;
+
         assert((obj_surface->size & 0x3f) == 0);
         obj_surface->private_data = gen7_vc1_surface;
     }
@@ -1547,25 +1586,29 @@ gen8_mfd_vc1_pic_state(VADriverContextP ctx,
             brfd = 0;
     }
 
-    overlap = 0;
-    if (profile != GEN7_VC1_ADVANCED_PROFILE){
-        if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
-            pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) {
-            overlap = 1; 
-        }
-    }else {
-        if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE &&
-             pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
-              overlap = 1; 
-        }
-        if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE ||
-            pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){
-             if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
-                overlap = 1; 
-             } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
-                        va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
-                 overlap = 1;
-             }
+    overlap = pic_param->sequence_fields.bits.overlap;
+
+    if (overlap) {
+        overlap = 0;
+        if (profile != GEN7_VC1_ADVANCED_PROFILE){
+            if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
+                pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) {
+                overlap = 1;
+            }
+        }else {
+            if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE &&
+                pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
+                overlap = 1;
+            }
+            if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE ||
+                pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){
+                if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
+                    overlap = 1;
+                } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
+                           va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
+                    overlap = 1;
+                }
+            }
         }
     } 
 
@@ -1655,9 +1698,6 @@ gen8_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
 
     assert(decode_state->pic_param && decode_state->pic_param->buffer);
     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
-
-    assert(decode_state->pic_param && decode_state->pic_param->buffer);
-    pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
 
     BEGIN_BCS_BATCH(batch, 6);
@@ -1683,6 +1723,7 @@ gen8_mfd_vc1_directmode_state(VADriverContextP ctx,
                               struct decode_state *decode_state,
                               struct gen7_mfd_context *gen7_mfd_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
     struct object_surface *obj_surface;
     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
@@ -1703,24 +1744,26 @@ gen8_mfd_vc1_directmode_state(VADriverContextP ctx,
     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2));
 
     if (dmv_write_buffer)
-        OUT_BCS_RELOC(batch, dmv_write_buffer,
+        OUT_BCS_RELOC64(batch, dmv_write_buffer,
                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-    else
+    else {
+        OUT_BCS_BATCH(batch, 0);
         OUT_BCS_BATCH(batch, 0);
+    }
 
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
     if (dmv_read_buffer)
-        OUT_BCS_RELOC(batch, dmv_read_buffer,
+        OUT_BCS_RELOC64(batch, dmv_read_buffer,
                       I915_GEM_DOMAIN_INSTRUCTION, 0,
                       0);
-    else
+    else {
         OUT_BCS_BATCH(batch, 0);
+        OUT_BCS_BATCH(batch, 0);
+    }
     
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
                   
     ADVANCE_BCS_BATCH(batch);
 }
@@ -1851,9 +1894,10 @@ gen8_mfd_jpeg_decode_init(VADriverContextP ctx,
 
     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
 
-    if (pic_param->num_components == 1)
+    if (pic_param->num_components == 1) {
         subsampling = SUBSAMPLE_YUV400;
-    else if (pic_param->num_components == 3) {
+        fourcc = VA_FOURCC_Y800;
+    } else if (pic_param->num_components == 3) {
         int h1 = pic_param->components[0].h_sampling_factor;
         int h2 = pic_param->components[1].h_sampling_factor;
         int h3 = pic_param->components[2].h_sampling_factor;
@@ -1885,7 +1929,7 @@ gen8_mfd_jpeg_decode_init(VADriverContextP ctx,
                    v1 == 2 && v2 == 2 && v3 == 2) {
             subsampling = SUBSAMPLE_YUV422H;
             fourcc = VA_FOURCC_422H;
-        } else if (h2 == 2 && h2 == 2 && h3 == 2 &&
+        } else if (h1 == 2 && h2 == 2 && h3 == 2 &&
                    v1 == 2 && v2 == 1 && v3 == 1) {
             subsampling = SUBSAMPLE_YUV422V;
             fourcc = VA_FOURCC_422V;
@@ -2273,12 +2317,11 @@ gen8_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
 
     BEGIN_BCS_BATCH(batch, 61);
     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
-    OUT_BCS_RELOC(batch,
+    OUT_BCS_RELOC64(batch,
                   obj_surface->bo,
                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                   0);
-       OUT_BCS_BATCH(batch, 0);
-       OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
     
 
     OUT_BCS_BATCH(batch, 0); /* post deblocking */
@@ -2294,12 +2337,12 @@ gen8_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
        OUT_BCS_BATCH(batch, 0);
 
        /* the DW 13-15 is for intra row store scratch */
-    OUT_BCS_RELOC(batch,
+    OUT_BCS_RELOC64(batch,
                   intra_bo,
                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                   0);
-       OUT_BCS_BATCH(batch, 0);
-       OUT_BCS_BATCH(batch, 0);
+
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
        /* the DW 16-18 is for deblocking filter */ 
     OUT_BCS_BATCH(batch, 0);
@@ -2351,20 +2394,18 @@ gen8_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
     BEGIN_BCS_BATCH(batch, 10);
     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
 
-    OUT_BCS_RELOC(batch,
+    OUT_BCS_RELOC64(batch,
                   bsd_mpc_bo,
                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                   0);
 
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
-    OUT_BCS_RELOC(batch,
+    OUT_BCS_RELOC64(batch,
                   mpr_bo,
                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
                   0);
-    OUT_BCS_BATCH(batch, 0);
-    OUT_BCS_BATCH(batch, 0);
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
 
     OUT_BCS_BATCH(batch, 0);
     OUT_BCS_BATCH(batch, 0);
@@ -2474,12 +2515,11 @@ gen8_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
 
     BEGIN_BCS_BATCH(batch, 11);
     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
-    OUT_BCS_RELOC(batch,
+    OUT_BCS_RELOC64(batch,
                   gen7_mfd_context->jpeg_wa_slice_data_bo,
                   I915_GEM_DOMAIN_INSTRUCTION, 0,
                   0);
-    OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
-    OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);
     OUT_BCS_BATCH(batch, 0);
     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
     OUT_BCS_BATCH(batch, 0);
@@ -2786,6 +2826,7 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
                        struct decode_state *decode_state,
                        struct gen7_mfd_context *gen7_mfd_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
     VAPictureParameterBufferVP8 *pic_param = (VAPictureParameterBufferVP8 *)decode_state->pic_param->buffer;
     VAIQMatrixBufferVP8 *iq_matrix = (VAIQMatrixBufferVP8 *)decode_state->iq_matrix->buffer;
@@ -2815,7 +2856,8 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
                   pic_param->pic_fields.bits.sign_bias_golden << 12 |
                   pic_param->pic_fields.bits.loop_filter_adj_enable << 11 |
                   pic_param->pic_fields.bits.mb_no_coeff_skip << 10 |
-                  pic_param->pic_fields.bits.update_mb_segmentation_map << 9 |
+                  (enable_segmentation &&
+                   pic_param->pic_fields.bits.update_mb_segmentation_map) << 9 |
                   pic_param->pic_fields.bits.segmentation_enabled << 8 |
                   (enable_segmentation &&
                    !pic_param->pic_fields.bits.update_mb_segmentation_map) << 7 |
@@ -2858,11 +2900,10 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
 
     /* CoeffProbability table for non-key frame, DW16-DW18 */
     if (probs_bo) {
-        OUT_BCS_RELOC(batch, probs_bo,
+        OUT_BCS_RELOC64(batch, probs_bo,
                       0, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-        OUT_BCS_BATCH(batch, 0);
-        OUT_BCS_BATCH(batch, 0);
+        OUT_BCS_BATCH(batch, i965->intel.mocs_state);
     } else {
         OUT_BCS_BATCH(batch, 0);
         OUT_BCS_BATCH(batch, 0);
@@ -2916,11 +2957,10 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
 
     /* segmentation id stream base address, DW35-DW37 */
     if (enable_segmentation) {
-        OUT_BCS_RELOC(batch, gen7_mfd_context->segmentation_buffer.bo,
+        OUT_BCS_RELOC64(batch, gen7_mfd_context->segmentation_buffer.bo,
                       0, I915_GEM_DOMAIN_INSTRUCTION,
                       0);
-        OUT_BCS_BATCH(batch, 0);
-        OUT_BCS_BATCH(batch, 0);
+        OUT_BCS_BATCH(batch, i965->intel.mocs_state);
     }
     else {
         OUT_BCS_BATCH(batch, 0);
@@ -2966,13 +3006,13 @@ gen8_mfd_vp8_bsd_object(VADriverContextP ctx,
                   pic_param->bool_coder_ctx.value << 24 | /* Partition 0 Count Entropy Value */
                   0);
 
-    OUT_BCS_BATCH(batch, partition_size_0);
+    OUT_BCS_BATCH(batch, partition_size_0 + 1);
     OUT_BCS_BATCH(batch, offset);
     //partion sizes in bytes are present after the above first partition when there are more than one token partition
     offset += (partition_size_0 + 3 * (slice_param->num_of_partitions - 2));
     for (i = 1; i < 9; i++) {
         if (i < slice_param->num_of_partitions) {
-            OUT_BCS_BATCH(batch, slice_param->partition_size[i]);
+            OUT_BCS_BATCH(batch, slice_param->partition_size[i] + 1);
             OUT_BCS_BATCH(batch, offset);
         } else {
             OUT_BCS_BATCH(batch, 0);
@@ -2982,9 +3022,7 @@ gen8_mfd_vp8_bsd_object(VADriverContextP ctx,
         offset += slice_param->partition_size[i];
     }
 
-    OUT_BCS_BATCH(batch,
-                  1 << 31 | /* concealment method */
-                  0);
+    OUT_BCS_BATCH(batch, 0); /* concealment method */
 
     ADVANCE_BCS_BATCH(batch);
 }
@@ -3062,6 +3100,8 @@ gen8_mfd_decode_picture(VADriverContextP ctx,
     case VAProfileH264ConstrainedBaseline:
     case VAProfileH264Main:
     case VAProfileH264High:
+    case VAProfileH264StereoHigh:
+    case VAProfileH264MultiviewHigh:
         gen8_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
         break;
 
@@ -3093,8 +3133,11 @@ out:
 static void
 gen8_mfd_context_destroy(void *hw_context)
 {
+    VADriverContextP ctx;
     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
 
+    ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
+
     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
     gen7_mfd_context->post_deblocking_output.bo = NULL;
 
@@ -3121,6 +3164,13 @@ gen8_mfd_context_destroy(void *hw_context)
 
     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
 
+    if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
+        i965_DestroySurfaces(ctx,
+                             &gen7_mfd_context->jpeg_wa_surface_id,
+                             1);
+        gen7_mfd_context->jpeg_wa_surface_object = NULL;
+    }
+
     intel_batchbuffer_free(gen7_mfd_context->base.batch);
     free(gen7_mfd_context);
 }
@@ -3141,6 +3191,9 @@ gen8_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
     int i;
 
+    if (!gen7_mfd_context)
+        return NULL;
+
     gen7_mfd_context->base.destroy = gen8_mfd_context_destroy;
     gen7_mfd_context->base.run = gen8_mfd_decode_picture;
     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
@@ -3162,10 +3215,14 @@ gen8_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
     case VAProfileH264ConstrainedBaseline:
     case VAProfileH264Main:
     case VAProfileH264High:
+    case VAProfileH264StereoHigh:
+    case VAProfileH264MultiviewHigh:
         gen8_mfd_avc_context_init(ctx, gen7_mfd_context);
         break;
     default:
         break;
     }
+
+    gen7_mfd_context->driver_context = ctx;
     return (struct hw_context *)gen7_mfd_context;
 }