#define GEN9_MAX_REF_SURFACES 8
#define GEN9_MAX_MV_TEMPORAL_BUFFERS (GEN9_MAX_REF_SURFACES + 1)
+#define GEN9_HEVC_NUM_MAX_REF_L0 3
+#define GEN9_HEVC_NUM_MAX_REF_L1 1
+
enum GEN9_HEVC_ENC_SURFACE_TYPE {
GEN9_HEVC_ENC_SURFACE_RECON = 0,
GEN9_HEVC_ENC_SURFACE_SOURCE = 1
int pak_obj_size;
int cu_record_size;
int pic_state_size;
- int slice_batch_offset[NUM_SLICES];
- int slice_start_lcu[NUM_SLICES];
+ int slice_batch_offset[I965_MAX_NUM_SLICE];
+ int slice_start_lcu[I965_MAX_NUM_SLICE];
struct hevc_encode_status_buffer status_buffer;
enum HEVC_TU_MODE tu_mode;
unsigned int parallel_brc;
unsigned int num_roi;
+ unsigned int roi_value_is_qp_delta;
unsigned int max_delta_qp;
unsigned int min_delta_qp;
struct intel_roi roi[MAX_HEVC_MAX_NUM_ROI];