ENC:disable SVC feature of AVC encoder on SKL/APL/KBL

[android-x86/hardware-intel-common-vaapi.git] / src / gen9_vme.c

diff --git a/src/gen9_vme.c b/src/gen9_vme.c
index fab80ce..656b322 100644 (file)
--- a/src/gen9_vme.c
+++ b/src/gen9_vme.c
@@ -44,6 +44,7 @@
 #include "intel_media.h"
 #include "gen9_vp9_encapi.h"
 #include "i965_post_processing.h"
+#include "i965_encoder_api.h"
 
 #ifdef SURFACE_STATE_PADDED_SIZE
 #undef SURFACE_STATE_PADDED_SIZE
@@ -768,11 +769,10 @@ static void gen9_vme_pipeline_programing(VADriverContextP ctx,
     gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
     BEGIN_BATCH(batch, 3);
     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
-    OUT_RELOC(batch,
+    OUT_RELOC64(batch,
               vme_context->vme_batchbuffer.bo,
               I915_GEM_DOMAIN_COMMAND, 0,
               0);
-    OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
     gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
@@ -1162,12 +1162,11 @@ gen9_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
     gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
     BEGIN_BATCH(batch, 4);
     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
-    OUT_RELOC(batch,
+    OUT_RELOC64(batch,
               vme_context->vme_batchbuffer.bo,
               I915_GEM_DOMAIN_COMMAND, 0,
               0);
     OUT_BATCH(batch, 0);
-    OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
     gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
@@ -1303,12 +1302,11 @@ gen9_vme_vp8_pipeline_programing(VADriverContextP ctx,
     gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
     BEGIN_BATCH(batch, 4);
     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
-    OUT_RELOC(batch,
+    OUT_RELOC64(batch,
               vme_context->vme_batchbuffer.bo,
               I915_GEM_DOMAIN_COMMAND, 0,
               0);
     OUT_BATCH(batch, 0);
-    OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
     gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
@@ -1432,7 +1430,7 @@ gen9_vme_hevc_surface_setup(VADriverContextP ctx,
 
     if((pSequenceParameter->seq_fields.bits.bit_depth_luma_minus8 > 0)
         || (pSequenceParameter->seq_fields.bits.bit_depth_chroma_minus8 > 0)) {
-        hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
+        hevc_encoder_surface = (GenHevcSurface *)encode_state->reconstructed_object->private_data;
         assert(hevc_encoder_surface);
         obj_surface = hevc_encoder_surface->nv12_surface_obj;
     }
@@ -1737,11 +1735,10 @@ static void gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
     gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
     BEGIN_BATCH(batch, 3);
     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
-    OUT_RELOC(batch,
+    OUT_RELOC64(batch,
               vme_context->vme_batchbuffer.bo,
               I915_GEM_DOMAIN_COMMAND, 0,
               0);
-    OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
     gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
@@ -1752,7 +1749,9 @@ static void gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
 static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx,
                             struct intel_encoder_context *encoder_context,
                             struct encode_state *encode_state,
-                            struct object_surface *input_obj_surface)
+                            struct object_surface *input_obj_surface,
+                            struct object_surface *output_obj_surface,
+                            int set_flag)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
@@ -1765,7 +1764,7 @@ static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx,
 
     uint32_t size;
 
-    obj_surface = input_obj_surface;
+    obj_surface = output_obj_surface;
     assert(obj_surface && obj_surface->bo);
 
     if (obj_surface->private_data == NULL) {
@@ -1807,7 +1806,7 @@ static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx,
         rect.width = obj_surface->orig_width;
         rect.height = obj_surface->orig_height;
 
-        src_surface.base = (struct object_base *)obj_surface;
+        src_surface.base = (struct object_base *)input_obj_surface;
         src_surface.type = I965_SURFACE_TYPE_SURFACE;
         src_surface.flags = I965_SURFACE_FLAG_FRAME;
 
@@ -1840,8 +1839,11 @@ static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx,
             &dst_surface,
             &rect);
         assert(status == VA_STATUS_SUCCESS);
-        hevc_encoder_surface->has_p010_to_nv12_done = 1;
+
+        if (set_flag)
+            hevc_encoder_surface->has_p010_to_nv12_done = 1;
     }
+
     return VA_STATUS_SUCCESS;
 }
 
@@ -1856,12 +1858,8 @@ static VAStatus gen9_intel_hevc_input_check(VADriverContextP ctx,
     int i;
     int fourcc;
 
-    obj_surface = SURFACE(encode_state->current_render_target);
+    obj_surface = SURFACE(encoder_context->input_yuv_surface);
     assert(obj_surface && obj_surface->bo);
-    hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
-    if(hevc_encoder_surface)
-        hevc_encoder_surface->has_p010_to_nv12_done = 0;
-    gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface);
 
     fourcc = obj_surface->fourcc;
     /* Setup current frame and current direct mv buffer*/
@@ -1873,8 +1871,9 @@ static VAStatus gen9_intel_hevc_input_check(VADriverContextP ctx,
     hevc_encoder_surface = NULL;
     hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
     if(hevc_encoder_surface)
-        hevc_encoder_surface->has_p010_to_nv12_done = 1;
-    gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface);
+        hevc_encoder_surface->has_p010_to_nv12_done = 0;
+    gen9_intel_init_hevc_surface(ctx, encoder_context, encode_state, encode_state->input_yuv_object,
+                                 obj_surface, 0);
 
     /* Setup reference frames and direct mv buffers*/
     for (i = 0; i < MAX_HCP_REFERENCE_SURFACES; i++) {
@@ -1884,7 +1883,8 @@ static VAStatus gen9_intel_hevc_input_check(VADriverContextP ctx,
             mfc_context->reference_surfaces[i].bo = obj_surface->bo;
             dri_bo_reference(obj_surface->bo);
 
-            gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface);
+            gen9_intel_init_hevc_surface(ctx, encoder_context, encode_state, obj_surface,
+                                         obj_surface, 1);
         } else {
             break;
         }
@@ -1976,8 +1976,11 @@ gen9_vme_context_destroy(void *context)
     free(vme_context);
 }
 
+extern Bool i965_encoder_vp8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
 Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct gen6_vme_context *vme_context;
     struct i965_kernel *vme_kernel_list = NULL;
     int i965_kernel_num;
@@ -1990,6 +1993,11 @@ Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e
         return True;
     } else if (encoder_context->codec == CODEC_VP9) {
         return gen9_vp9_vme_context_init(ctx, encoder_context);
+    } else if (encoder_context->codec == CODEC_VP8) {
+        return i965_encoder_vp8_vme_context_init(ctx, encoder_context);
+    } else if (encoder_context->codec == CODEC_H264 ||
+               encoder_context->codec == CODEC_H264_MVC) {
+        return gen9_avc_vme_context_init(ctx, encoder_context);
     }
 
     vme_context = calloc(1, sizeof(struct gen6_vme_context));
@@ -2037,7 +2045,12 @@ Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e
     vme_context->gpe_context.sampler.entry_size = 0;
     vme_context->gpe_context.sampler.max_entries = 0;
 
-    vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
+    if (i965->intel.eu_total > 0) {
+        vme_context->gpe_context.vfe_state.max_num_threads = 6 *
+                              i965->intel.eu_total;
+    } else
+        vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
+
     vme_context->gpe_context.vfe_state.num_urb_entries = 64;
     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
     vme_context->gpe_context.vfe_state.urb_entry_size = 16;