#include <intel_bufmgr.h>
#include "i965_defines.h"
-#include "i965_drv_video.h"
#include "i965_structs.h"
#define MAX_GPE_KERNELS 32
unsigned int sampler_offset;
};
+#define PIPE_CONTROL_FLUSH_NONE 0
+#define PIPE_CONTROL_FLUSH_WRITE_CACHE 1
+#define PIPE_CONTROL_FLUSH_READ_CACHE 2
+
+struct gpe_pipe_control_parameter
+{
+ dri_bo *bo;
+ unsigned int offset;
+ unsigned int flush_mode;
+ unsigned int disable_cs_stall;
+ unsigned int dw0;
+ unsigned int dw1;
+};
+
struct i965_gpe_context
{
struct {
struct intel_batchbuffer *batch,
struct gpe_mi_store_data_imm_parameter *params);
-void gen9_gpe_mi_store_register_mem(VADriverContextP ctx,
+void gen8_gpe_mi_store_register_mem(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_mi_store_register_mem_parameter *params);
-void gen9_gpe_mi_load_register_mem(VADriverContextP ctx,
+void gen8_gpe_mi_load_register_mem(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_mi_load_register_mem_parameter *params);
-void gen9_gpe_mi_load_register_imm(VADriverContextP ctx,
+void gen8_gpe_mi_load_register_imm(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_mi_load_register_imm_parameter *params);
-void gen9_gpe_mi_load_register_reg(VADriverContextP ctx,
+void gen8_gpe_mi_load_register_reg(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_mi_load_register_reg_parameter *params);
extern void
intel_vpp_init_media_object_walker_parameter(struct intel_vpp_kernel_walker_parameter *kernel_walker_param,
struct gpe_media_object_walker_parameter *walker_param);
+extern void
+gen8_gpe_reset_binding_table(VADriverContextP ctx, struct i965_gpe_context *gpe_context);
+
+extern void
+gen8_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
+ struct i965_gpe_surface *gpe_surface,
+ int index);
+
+extern void
+gen8_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_conditional_batch_buffer_end_parameter *param);
+
+extern void
+gen8_gpe_pipe_control(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_pipe_control_parameter *param);
+
+struct i965_gpe_table
+{
+ void (*context_init)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context);
+
+ void (*context_destroy)(struct i965_gpe_context *gpe_context);
+
+ void (*context_add_surface)(struct i965_gpe_context *gpe_context,
+ struct i965_gpe_surface *gpe_surface,
+ int index);
+
+ void (*reset_binding_table)(VADriverContextP ctx, struct i965_gpe_context *gpe_context);
+
+ void (*load_kernels)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_kernel *kernel_list,
+ unsigned int num_kernels);
+
+ void (*setup_interface_data)(VADriverContextP ctx, struct i965_gpe_context *gpe_context);
+
+ void (*set_dynamic_buffer)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct gpe_dynamic_state_parameter *ds);
+
+ void (*media_object)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct intel_batchbuffer *batch,
+ struct gpe_media_object_parameter *param);
+
+ void (*media_object_walker)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct intel_batchbuffer *batch,
+ struct gpe_media_object_walker_parameter *param);
+
+ void (*media_state_flush)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct intel_batchbuffer *batch);
+
+
+ void (*pipe_control)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_pipe_control_parameter *param);
+
+ void (*pipeline_end)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct intel_batchbuffer *batch); // only available on gen9+
+
+ void (*pipeline_setup)(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct intel_batchbuffer *batch);
+
+ void (*mi_conditional_batch_buffer_end)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_conditional_batch_buffer_end_parameter *param);
+
+ void (*mi_batch_buffer_start)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_batch_buffer_start_parameter *params);
+
+ void (*mi_load_register_reg)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_reg_parameter *params);
+
+ void (*mi_load_register_imm)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_imm_parameter *params);
+
+ void (*mi_load_register_mem)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_mem_parameter *params);
+
+
+ void (*mi_store_register_mem)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_store_register_mem_parameter *params);
+
+ void (*mi_store_data_imm)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_store_data_imm_parameter *params);
+
+ void (*mi_flush_dw)(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_flush_dw_parameter *params);
+};
+
+extern bool
+i965_gpe_table_init(VADriverContextP ctx);
+
+extern void
+i965_gpe_table_terminate(VADriverContextP ctx);
#endif /* _I965_GPE_UTILS_H_ */