Add a new CFL PCI ID

[android-x86/hardware-intel-common-vaapi.git] / src / i965_pciids.h

diff --git a/src/i965_pciids.h b/src/i965_pciids.h
index 1ea3c98..292ea6e 100644 (file)
--- a/src/i965_pciids.h
+++ b/src/i965_pciids.h
@@ -163,23 +163,62 @@ CHIPSET(0x1A84, bxt, bxt,       "Intel(R) Broxton")
 CHIPSET(0x1A85, bxt, bxt,       "Intel(R) Broxton")
 CHIPSET(0x5A84, bxt, bxt,       "Intel(R) Broxton")
 CHIPSET(0x5A85, bxt, bxt,       "Intel(R) Broxton")
-CHIPSET(0x5916, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5913, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5906, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5926, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5921, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5915, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x590E, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x591E, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5912, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5917, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5902, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x591B, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x593B, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x590B, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x591A, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x590A, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x591D, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5908, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5923, kbl, kbl,       "Intel(R) Kabylake")
-CHIPSET(0x5927, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5916, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5913, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5906, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5926, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5921, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5915, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x590E, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x591E, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5912, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5917, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x591C, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5902, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x591B, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x593B, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x590B, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x591A, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x590A, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x591D, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5908, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5923, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x5927, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x87C0, kbl, kbl,       "Intel(R) Kaby Lake")
+CHIPSET(0x3184, glk, glk,       "Intel(R) Gemini Lake")
+CHIPSET(0x3185, glk, glk,       "Intel(R) Gemini Lake")
+CHIPSET(0x3EA0, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA1, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA2, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA3, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA4, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA5, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA6, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA7, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA8, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3EA9, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E90, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E91, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E92, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E93, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E94, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E96, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E98, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E99, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E9A, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x3E9B, cfl, cfl,       "Intel(R) Coffee Lake")
+CHIPSET(0x5A40, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A41, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A42, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A44, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A45, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A49, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A4A, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A50, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A51, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A52, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A54, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A55, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A59, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A5A, cnl, cnl,       "Intel(R) CannonLake")
+CHIPSET(0x5A5C, cnl, cnl,       "Intel(R) CannonLake")