#ifndef __I965_POST_PROCESSING_H__
#define __I965_POST_PROCESSING_H__
-#define MAX_PP_SURFACES 48
+#include "i965_vpp_avs.h"
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+#include "i965_gpe_utils.h"
-#define I965_PP_FLAG_TOP_FIELD 1
-#define I965_PP_FLAG_BOTTOM_FIELD 2
-#define I965_PP_FLAG_MCDI 4
-#define I965_PP_FLAG_AVS 8
+#define MAX_PP_SURFACES 48
+
+struct i965_gpe_context;
enum
{
PP_PL3_LOAD_SAVE_PA,
PP_PA_LOAD_SAVE_NV12,
PP_PA_LOAD_SAVE_PL3,
+ PP_PA_LOAD_SAVE_PA,
PP_RGBX_LOAD_SAVE_NV12,
PP_NV12_LOAD_SAVE_RGBX,
NUM_PP_MODULES,
struct pp_avs_context
{
+ AVSState state;
int dest_x; /* in pixel */
int dest_y; /* in pixel */
int dest_w;
float horiz_range;
};
+enum {
+ DNDI_FRAME_IN_CURRENT = 0,
+ DNDI_FRAME_IN_PREVIOUS,
+ DNDI_FRAME_IN_STMM,
+ DNDI_FRAME_OUT_STMM,
+ DNDI_FRAME_OUT_CURRENT,
+ DNDI_FRAME_OUT_PREVIOUS,
+ DNDI_FRAME_STORE_COUNT
+};
+
+typedef struct dndi_frame_store {
+ struct object_surface *obj_surface;
+ VASurfaceID surface_id; /* always relative to the input surface */
+ unsigned int is_scratch_surface : 1;
+} DNDIFrameStore;
+
struct pp_dndi_context
{
int dest_w;
int dest_h;
+ DNDIFrameStore frame_store[DNDI_FRAME_STORE_COUNT];
+
+ /* Temporary flags live until the current picture is processed */
+ unsigned int is_di_enabled : 1;
+ unsigned int is_di_adv_enabled : 1;
+ unsigned int is_first_frame : 1;
+ unsigned int is_second_field : 1;
};
struct pp_dn_context
{
int dest_w;
int dest_h;
+ dri_bo *stmm_bo;
};
+struct i965_post_processing_context;
+
struct pp_module
{
struct i965_kernel kernel;
struct {
/* r2.0 */
- unsigned int pad3;
+ /* Indicates whether the rgb is swapped for the src surface
+ * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
+ */
+ unsigned int src_avs_rgb_swap:1;
+ unsigned int pad3:31;
/* r2.1 */
unsigned int pad2:16;
unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
- unsigned int src_avs_rgb_swap:1;
- /* Indicates whether the rgb is swapped for the src surface
- * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
- */
+ unsigned int ief_enable:1;
unsigned int avs_wa_width:13;
/* 2.2 */
unsigned int di_destination_packed_y_component_offset:8;
unsigned int di_destination_packed_u_component_offset:8;
unsigned int di_destination_packed_v_component_offset:8;
- unsigned int pad0:8;
+ unsigned int alpha:8;
} grf2;
struct {
float sampler_load_horizontal_frame_origin;
unsigned int padx[7];
} grf6;
+
+ struct {
+ /* r7.0 -> r7.3 */
+ float coef_ry;
+ float coef_ru;
+ float coef_rv;
+ float coef_yd;
+
+ /* r7.4 -> r7.7 */
+ float coef_gy;
+ float coef_gu;
+ float coef_gv;
+ float coef_ud;
+ } grf7;
+
+ struct {
+ /* r8.0 -> r8.3 */
+ float coef_by;
+ float coef_bu;
+ float coef_bv;
+ float coef_vd;
+
+ /* r8.4 -> r8.7 */
+ unsigned int padx[4];
+ } grf8;
};
struct gen7_pp_inline_parameter
{
struct {
- /* r7.0 */
+ /* r9.0 */
unsigned int destination_block_horizontal_origin:16;
unsigned int destination_block_vertical_origin:16;
- /* r7.1: 0xffffffff */
+ /* r9.1: 0xffffffff */
unsigned int constant_0;
- /* r7.2 */
+ /* r9.2 */
unsigned int pad0;
- /* r7.3 */
+ /* r9.3 */
unsigned int pad1;
- /* r7.4 */
+ /* r9.4 */
float sampler_load_main_video_x_scaling_step;
- /* r7.5 */
+ /* r9.5 */
unsigned int pad2;
- /* r7.6: must be zero */
+ /* r9.6: must be zero */
unsigned int avs_vertical_block_number;
- /* r7.7: 0 */
+ /* r9.7: 0 */
unsigned int group_id_number;
- } grf7;
+ } grf9;
struct {
unsigned int padx[8];
- } grf8;
+ } grf10;
};
struct i965_post_processing_context
} urb;
struct {
- dri_bo *bo;
- } stmm;
-
- union {
- struct pp_load_save_context pp_load_save_context;
- struct pp_scaling_context pp_scaling_context;
- struct pp_avs_context pp_avs_context;
- struct pp_dndi_context pp_dndi_context;
- struct pp_dn_context pp_dn_context;
- } private_context;
+ unsigned int gpgpu_mode : 1;
+ unsigned int pad0 : 7;
+ unsigned int max_num_threads : 16;
+ unsigned int num_urb_entries : 8;
+ unsigned int urb_entry_size : 16;
+ unsigned int curbe_allocation_size : 16;
+ } vfe_gpu_state;
+
+ struct intel_vebox_context *vebox_proc_ctx;
+
+ struct pp_load_save_context pp_load_save_context;
+ struct pp_scaling_context pp_scaling_context;
+ struct pp_avs_context pp_avs_context;
+ struct pp_dndi_context pp_dndi_context;
+ struct pp_dn_context pp_dn_context;
+ void *private_context; /* pointer to the current private context */
+ void *pipeline_param; /* pointer to the pipeline parameter */
+ /**
+ * \ref Extra filter flags used as a fast path.
+ *
+ * This corresponds to vaPutSurface() flags, for direct rendering,
+ * or to VAProcPipelineParameterBuffer.filter_flags when the VPP
+ * interfaces are used. In the latter case, this is just a copy of
+ * that field.
+ */
+ unsigned int filter_flags;
int (*pp_x_steps)(void *private_context);
int (*pp_y_steps)(void *private_context);
unsigned int block_horizontal_mask_left:16;
unsigned int block_horizontal_mask_right:16;
unsigned int block_vertical_mask_bottom:8;
+
+ struct {
+ dri_bo *bo;
+ int bo_size;
+ unsigned int end_offset;
+ } instruction_state;
+
+ struct {
+ dri_bo *bo;
+ } indirect_state;
+
+ struct {
+ dri_bo *bo;
+ int bo_size;
+ unsigned int end_offset;
+ } dynamic_state;
+
+ unsigned int sampler_offset;
+ int sampler_size;
+ unsigned int idrt_offset;
+ int idrt_size;
+ unsigned int curbe_offset;
+ int curbe_size;
+
+ VAStatus (*intel_post_processing)(VADriverContextP ctx,
+ struct i965_post_processing_context *pp_context,
+ const struct i965_surface *src_surface,
+ const VARectangle *src_rect,
+ struct i965_surface *dst_surface,
+ const VARectangle *dst_rect,
+ int pp_index,
+ void * filter_param);
+ void (*finalize)(VADriverContextP ctx,
+ struct i965_post_processing_context *pp_context);
+
+
+ struct i965_gpe_context scaling_10bit_context;
+ int scaling_context_initialized;
};
struct i965_proc_context
{
struct hw_context base;
+ void *driver_context;
struct i965_post_processing_context pp_context;
};
VASurfaceID
i965_post_processing(
VADriverContextP ctx,
- VASurfaceID surface,
+ struct object_surface *obj_surface,
const VARectangle *src_rect,
const VARectangle *dst_rect,
- unsigned int flags,
- int *has_done_scaling
+ unsigned int va_flags,
+ int *has_done_scaling,
+ VARectangle *calibrated_rect
);
VAStatus
i965_scaling_processing(
VADriverContextP ctx,
- VASurfaceID src_surface_id,
+ struct object_surface *src_surface_obj,
const VARectangle *src_rect,
- VASurfaceID dst_surface_id,
+ struct object_surface *dst_surface_obj,
const VARectangle *dst_rect,
- unsigned int flags
+ unsigned int va_flags
);
VAStatus
bool
i965_post_processing_init(VADriverContextP ctx);
+
+extern VAStatus
+i965_proc_picture(VADriverContextP ctx,
+ VAProfile profile,
+ union codec_state *codec_state,
+ struct hw_context *hw_context);
+
#endif /* __I965_POST_PROCESSING_H__ */
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