typedef uint32_t xcb_visualid_t;
typedef uint32_t xcb_window_t;
-#define VK_USE_PLATFORM_XCB_KHR
-#define VK_USE_PLATFORM_WAYLAND_KHR
+struct anv_l3_config;
-#define VK_PROTOTYPES
#include <vulkan/vulkan.h>
#include <vulkan/vulkan_intel.h>
#include <vulkan/vk_icd.h>
#define MAX(a, b) ((a) > (b) ? (a) : (b))
static inline uint32_t
+align_down_npot_u32(uint32_t v, uint32_t a)
+{
+ return v - (v % a);
+}
+
+static inline uint32_t
align_u32(uint32_t v, uint32_t a)
{
assert(a != 0 && a == (a & -a));
uint32_t size);
void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
+struct anv_scratch_pool {
+ /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
+ struct anv_bo bos[16][MESA_SHADER_STAGES];
+};
+
+void anv_scratch_pool_init(struct anv_device *device,
+ struct anv_scratch_pool *pool);
+void anv_scratch_pool_finish(struct anv_device *device,
+ struct anv_scratch_pool *pool);
+struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
+ struct anv_scratch_pool *pool,
+ gl_shader_stage stage,
+ unsigned per_thread_scratch);
void *anv_resolve_entrypoint(uint32_t index);
anv_free(parent_alloc, data);
}
+struct anv_wsi_interaface;
+
+#define VK_ICD_WSI_PLATFORM_MAX 5
+
struct anv_physical_device {
VK_LOADER_DATA _loader_data;
struct anv_instance * instance;
uint32_t chipset_id;
- const char * path;
+ char path[20];
const char * name;
const struct brw_device_info * info;
uint64_t aperture_size;
struct brw_compiler * compiler;
struct isl_device isl_dev;
-};
+ int cmd_parser_version;
-struct anv_wsi_interaface;
-
-#define VK_ICD_WSI_PLATFORM_MAX 5
+ struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
+};
struct anv_instance {
VK_LOADER_DATA _loader_data;
uint32_t apiVersion;
int physicalDeviceCount;
struct anv_physical_device physicalDevice;
-
- struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
};
-VkResult anv_init_wsi(struct anv_instance *instance);
-void anv_finish_wsi(struct anv_instance *instance);
+VkResult anv_init_wsi(struct anv_physical_device *physical_device);
+void anv_finish_wsi(struct anv_physical_device *physical_device);
struct anv_meta_state {
VkAllocationCallbacks alloc;
struct {
VkRenderPass render_pass;
- /** Pipeline that copies from a 2D image. */
- VkPipeline pipeline_2d_src;
+ VkPipelineLayout img_p_layout;
+ VkDescriptorSetLayout img_ds_layout;
+ VkPipelineLayout buf_p_layout;
+ VkDescriptorSetLayout buf_ds_layout;
- VkPipelineLayout pipeline_layout;
- VkDescriptorSetLayout ds_layout;
+ /* Pipelines indexed by source and destination type. See the
+ * blit2d_src_type and blit2d_dst_type enums in anv_meta_blit2d.c to
+ * see what these mean.
+ */
+ VkPipeline pipelines[2][3];
} blit2d;
struct {
int context_id;
int fd;
bool can_chain_batches;
+ bool robust_buffer_access;
struct anv_bo_pool batch_bo_pool;
struct anv_queue queue;
- struct anv_block_pool scratch_block_pool;
+ struct anv_scratch_pool scratch_pool;
uint32_t default_mocs;
#define __anv_cmd_length_bias(cmd) cmd ## _length_bias
#define __anv_cmd_header(cmd) cmd ## _header
#define __anv_cmd_pack(cmd) cmd ## _pack
+#define __anv_reg_num(reg) reg ## _num
-#define anv_batch_emit(batch, cmd, ...) do { \
- void *__dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
- struct cmd __template = { \
- __anv_cmd_header(cmd), \
+#define anv_pack_struct(dst, struc, ...) do { \
+ struct struc __template = { \
__VA_ARGS__ \
}; \
- __anv_cmd_pack(cmd)(batch, __dst, &__template); \
- VG(VALGRIND_CHECK_MEM_IS_DEFINED(__dst, __anv_cmd_length(cmd) * 4)); \
+ __anv_cmd_pack(struc)(NULL, dst, &__template); \
+ VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
} while (0)
#define anv_batch_emitn(batch, n, cmd, ...) ({ \
VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
} while (0)
+#define anv_batch_emit(batch, cmd, name) \
+ for (struct cmd name = { __anv_cmd_header(cmd) }, \
+ *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
+ __builtin_expect(_dst != NULL, 1); \
+ ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
+ VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
+ _dst = NULL; \
+ }))
+
#define anv_state_pool_emit(pool, cmd, align, ...) ({ \
const uint32_t __size = __anv_cmd_length(cmd) * 4; \
struct anv_state __state = \
};
struct anv_descriptor_set_binding_layout {
+#ifndef NDEBUG
+ /* The type of the descriptors in this binding */
+ VkDescriptorType type;
+#endif
+
/* Number of array elements in this binding */
uint16_t array_size;
struct anv_descriptor_pool *pool,
struct anv_descriptor_set *set);
-#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT16_MAX
+#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
struct anv_pipeline_binding {
/* The descriptor set this surface corresponds to. The special value of
* ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
* to a color attachment and not a regular descriptor.
*/
- uint16_t set;
+ uint8_t set;
- /* Offset into the descriptor set or attachment list. */
- uint16_t offset;
+ /* Binding in the descriptor set */
+ uint8_t binding;
+
+ /* Index in the binding */
+ uint8_t index;
};
struct anv_pipeline_layout {
struct {
bool has_dynamic_offsets;
} stage[MESA_SHADER_STAGES];
+
+ unsigned char sha1[20];
};
struct anv_buffer {
};
typedef uint32_t anv_cmd_dirty_mask_t;
+enum anv_pipe_bits {
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
+ ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
+ ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
+ ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
+ ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
+ ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
+ ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
+ ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
+ ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
+ ANV_PIPE_CS_STALL_BIT = (1 << 20),
+
+ /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
+ * a flush has happened but not a CS stall. The next time we do any sort
+ * of invalidation we need to insert a CS stall at that time. Otherwise,
+ * we would have to CS stall on every flush which could be bad.
+ */
+ ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
+};
+
+#define ANV_PIPE_FLUSH_BITS ( \
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
+ ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
+
+#define ANV_PIPE_STALL_BITS ( \
+ ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
+ ANV_PIPE_DEPTH_STALL_BIT | \
+ ANV_PIPE_CS_STALL_BIT)
+
+#define ANV_PIPE_INVALIDATE_BITS ( \
+ ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
+ ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
+ ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
+ ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
+ ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
+ ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
+
struct anv_vertex_binding {
struct anv_buffer * buffer;
VkDeviceSize offset;
struct anv_cmd_state {
/* PIPELINE_SELECT.PipelineSelection */
uint32_t current_pipeline;
- uint32_t current_l3_config;
+ const struct anv_l3_config * current_l3_config;
uint32_t vb_dirty;
anv_cmd_dirty_mask_t dirty;
anv_cmd_dirty_mask_t compute_dirty;
+ enum anv_pipe_bits pending_pipe_bits;
uint32_t num_workgroups_offset;
struct anv_bo *num_workgroups_bo;
VkShaderStageFlags descriptors_dirty;
struct anv_framebuffer * framebuffer;
struct anv_render_pass * pass;
struct anv_subpass * subpass;
+ VkRect2D render_area;
uint32_t restart_index;
struct anv_vertex_binding vertex_bindings[MAX_VBS];
struct anv_descriptor_set * descriptors[MAX_SETS];
+ VkShaderStageFlags push_constant_stages;
struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
struct anv_state binding_tables[MESA_SHADER_STAGES];
struct anv_state samplers[MESA_SHADER_STAGES];
unsigned stage, struct anv_state *bt_state);
VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
unsigned stage, struct anv_state *state);
-uint32_t gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
-void gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
- uint32_t stages);
+uint32_t anv_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
const void *data, uint32_t size, uint32_t alignment);
anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
+void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
+ bool depth_clamp_enable);
void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
struct anv_shader_module *module,
const char *entrypoint,
+ const struct anv_pipeline_layout *pipeline_layout,
const VkSpecializationInfo *spec_info);
static inline gl_shader_stage
struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES];
bool use_repclear;
+ bool needs_data_cache;
const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
- uint32_t scratch_start[MESA_SHADER_STAGES];
- uint32_t total_scratch;
struct {
- uint8_t push_size[MESA_SHADER_FRAGMENT + 1];
uint32_t start[MESA_SHADER_GEOMETRY + 1];
uint32_t size[MESA_SHADER_GEOMETRY + 1];
uint32_t entries[MESA_SHADER_GEOMETRY + 1];
+ const struct anv_l3_config * l3_config;
+ uint32_t total_size;
} urb;
VkShaderStageFlags active_stages;
struct anv_state blend_state;
uint32_t vs_simd8;
uint32_t vs_vec4;
- uint32_t ps_simd8;
- uint32_t ps_simd16;
uint32_t ps_ksp0;
- uint32_t ps_ksp2;
- uint32_t ps_grf_start0;
- uint32_t ps_grf_start2;
uint32_t gs_kernel;
uint32_t cs_simd;
bool primitive_restart;
uint32_t topology;
- uint32_t cs_thread_width_max;
uint32_t cs_right_mask;
+ bool depth_clamp_enable;
+
struct {
uint32_t sf[7];
uint32_t depth_stencil_state[3];
int8_t color_attachment_count;
bool use_repclear;
- bool disable_viewport;
- bool disable_scissor;
bool disable_vs;
bool use_rectlist;
};
VkPipeline *pPipeline);
struct anv_format_swizzle {
- unsigned r:2;
- unsigned g:2;
- unsigned b:2;
- unsigned a:2;
+ enum isl_channel_select r:4;
+ enum isl_channel_select g:4;
+ enum isl_channel_select b:4;
+ enum isl_channel_select a:4;
};
struct anv_format {
- const VkFormat vk_format;
- const char *name;
- enum isl_format isl_format; /**< RENDER_SURFACE_STATE.SurfaceFormat */
- const struct isl_format_layout *isl_layout;
+ enum isl_format isl_format:16;
struct anv_format_swizzle swizzle;
- bool has_depth;
- bool has_stencil;
};
-const struct anv_format *
-anv_format_for_vk_format(VkFormat format);
+struct anv_format
+anv_get_format(const struct brw_device_info *devinfo, VkFormat format,
+ VkImageAspectFlags aspect, VkImageTiling tiling);
-enum isl_format
-anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect,
- VkImageTiling tiling, struct anv_format_swizzle *swizzle);
-
-static inline bool
-anv_format_is_color(const struct anv_format *format)
+static inline enum isl_format
+anv_get_isl_format(const struct brw_device_info *devinfo, VkFormat vk_format,
+ VkImageAspectFlags aspect, VkImageTiling tiling)
{
- return !format->has_depth && !format->has_stencil;
+ return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
}
-static inline bool
-anv_format_is_depth_or_stencil(const struct anv_format *format)
-{
- return format->has_depth || format->has_stencil;
-}
+void
+anv_compute_urb_partition(struct anv_pipeline *pipeline);
+
+void
+anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline);
/**
* Subsurface of an anv_image.
* of the actual surface formats.
*/
VkFormat vk_format;
- const struct anv_format *format;
+ VkImageAspectFlags aspects;
VkExtent3D extent;
uint32_t levels;
uint32_t array_size;
* Image subsurfaces
*
* For each foo, anv_image::foo_surface is valid if and only if
- * anv_image::format has a foo aspect.
+ * anv_image::aspects has a foo aspect.
*
* The hardware requires that the depth buffer and stencil buffer be
* separate surfaces. From Vulkan's perspective, though, depth and stencil
struct anv_device *device,
const VkImageViewCreateInfo* pCreateInfo,
struct anv_cmd_buffer *cmd_buffer,
- uint32_t offset,
VkImageUsageFlags usage_mask);
struct anv_buffer_view {
struct brw_image_param storage_image_param;
};
-const struct anv_format *
-anv_format_for_descriptor_type(VkDescriptorType type);
+void anv_buffer_view_init(struct anv_buffer_view *view,
+ struct anv_device *device,
+ const VkBufferViewCreateInfo* pCreateInfo,
+ struct anv_cmd_buffer *cmd_buffer);
+
+enum isl_format
+anv_isl_format_for_descriptor_type(VkDescriptorType type);
static inline struct VkExtent3D
anv_sanitize_image_extent(const VkImageType imageType,
};
struct anv_render_pass_attachment {
- const struct anv_format *format;
+ VkFormat format;
uint32_t samples;
VkAttachmentLoadOp load_op;
VkAttachmentLoadOp stencil_load_op;
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