#define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
+#define MI_FLUSH_DW2 (CMD_MI | (0x26 << 23) | 0x3)
#define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
+#define MI_FLUSH_DW_NOWRITE (0 << 14)
+#define MI_FLUSH_DW_WRITE_QWORD (1 << 14)
+#define MI_FLUSH_DW_WRITE_TIME (3 << 14)
+
+#define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23))
+
+#define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
+
+#define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
+
+#define MI_LOAD_REGISTER_MEM (CMD_MI | (0x29 << 23))
+
+#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
+
+#define MI_MATH (CMD_MI | (0x1A << 23))
+
+#define MI_CONDITIONAL_BATCH_BUFFER_END (CMD_MI | (0x36 << 23))
+#define MI_COMPARE_MASK_MODE_ENANBLED (1 << 19)
#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
#define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
#define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
#define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
#define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
+#define CMD_PIPE_CONTROL_FLUSH_ENABLE (1 << 7)
#define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
#define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
#define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
#define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
#define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
+#define CMD_PIPE_CONTROL_GLOBAL_GTT_GEN8 (1 << 24)
+#define CMD_PIPE_CONTROL_LOCAL_PGTT_GEN8 (0 << 24)
+#define CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8 (1 << 4)
+#define CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8 (1 << 3)
+#define CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8 (1 << 2)
struct intel_batchbuffer;
#define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
#define CLAMP(min, max, a) ((a) < (min) ? (min) : ((a) > (max) ? (max) : (a)))
+#define ALIGN_FLOOR(i, n) ((i) & ~((n) - 1))
+
#define Bool int
#define True 1
#define False 0
} \
} while (0)
-struct intel_device_info
-{
+struct intel_device_info {
int gen;
int gt;
unsigned int is_skylake : 1; /* gen9 */
unsigned int is_broxton : 1; /* gen9 */
unsigned int is_kabylake : 1; /* gen9p5 */
+ unsigned int is_glklake : 1; /* gen9p5 lp*/
};
-struct intel_driver_data
-{
+struct intel_driver_data {
int fd;
int device_id;
int revision;
unsigned int has_blt : 1; /* Flag: has BLT unit? */
unsigned int has_vebox : 1; /* Flag: has VEBOX unit */
unsigned int has_bsd2 : 1; /* Flag: has the second BSD video ring unit */
+ unsigned int has_huc : 1; /* Flag: has a fully loaded HuC firmware? */
+
+ int eu_total;
const struct intel_device_info *device_info;
+ unsigned int mocs_state;
};
bool intel_driver_init(VADriverContextP ctx);
return (struct intel_driver_data *)ctx->pDriverData;
}
-struct intel_region
-{
+struct intel_region {
int x;
int y;
unsigned int width;
#define IS_KBL(device_info) (device_info->is_kabylake)
+#define IS_GLK(device_info) (device_info->is_glklake)
+
#endif /* _INTEL_DRIVER_H_ */