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i965: new integrated graphics chipset support
[android-x86/external-mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_line.c
index 8318227..7d51cdd 100644 (file)
@@ -130,6 +130,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    struct brw_instruction *plane_loop;
    struct brw_instruction *plane_active;
    struct brw_instruction *is_negative;
+   struct brw_instruction *is_neg2;
    struct brw_instruction *not_culled;
    struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
 
@@ -146,6 +147,16 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    brw_clip_init_planes(c);
    brw_clip_init_clipmask(c);
 
+   /* -ve rhw workaround */
+   if (!BRW_IS_IGD(p->brw)) {
+      brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+      brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
+              brw_imm_ud(1<<20));
+      brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
+   }
+
+   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
    plane_loop = brw_DO(p, BRW_EXECUTE_1);
    {
       /* if (planemask & 1)
@@ -183,13 +194,20 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
            /* Coming back in.  We know that both cannot be negative
             * because the line would have been culled in that case.
             */
-           brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
-           brw_math_invert(p, c->reg.t, c->reg.t);
-           brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
 
-           brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
-           brw_MOV(p, c->reg.t0, c->reg.t);
-           brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+           /* If both are positive, do nothing */
+             brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
+             is_neg2 = brw_IF(p, BRW_EXECUTE_1);
+             {
+               brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
+               brw_math_invert(p, c->reg.t, c->reg.t);
+               brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
+
+               brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
+               brw_MOV(p, c->reg.t0, c->reg.t);
+               brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+            }
+            brw_ENDIF(p, is_neg2);
         }
         brw_ENDIF(p, is_negative);      
       }