return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
}
+#define ALU3(op) \
+ fs_inst * \
+ fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
+ { \
+ return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
+ }
+
ALU1(NOT)
ALU1(MOV)
ALU1(FRC)
ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
+ALU3(LRP)
/** Gen4 predicated IF. */
fs_inst *
return instructions;
}
+/**
+ * A helper for MOV generation for fixing up broken hardware SEND dependency
+ * handling.
+ */
+fs_inst *
+fs_visitor::DEP_RESOLVE_MOV(int grf)
+{
+ fs_inst *inst = MOV(brw_null_reg(), fs_reg(GRF, grf, BRW_REGISTER_TYPE_F));
+
+ inst->ir = NULL;
+ inst->annotation = "send dependency resolve";
+
+ /* The caller always wants uncompressed to emit the minimal extra
+ * dependencies, and to avoid having to deal with aligning its regs to 2.
+ */
+ inst->force_uncompressed = true;
+
+ return inst;
+}
+
bool
fs_inst::equals(fs_inst *inst)
{
}
bool
+fs_inst::is_control_flow()
+{
+ switch (opcode) {
+ case BRW_OPCODE_DO:
+ case BRW_OPCODE_WHILE:
+ case BRW_OPCODE_IF:
+ case BRW_OPCODE_ELSE:
+ case BRW_OPCODE_ENDIF:
+ case BRW_OPCODE_BREAK:
+ case BRW_OPCODE_CONTINUE:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
fs_inst::is_send_from_grf()
{
- return opcode == FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7;
+ return (opcode == FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7 ||
+ (opcode == FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD &&
+ src[1].file == GRF));
}
bool
* link time.
*/
return 0;
- default:
+ case GLSL_TYPE_VOID:
+ case GLSL_TYPE_ERROR:
+ case GLSL_TYPE_INTERFACE:
assert(!"not reached");
- return 0;
+ break;
}
+
+ return 0;
}
fs_reg
{
current_annotation = "shader time end";
- enum shader_time_shader_type type;
+ enum shader_time_shader_type type, written_type, reset_type;
if (dispatch_width == 8) {
type = ST_FS8;
+ written_type = ST_FS8_WRITTEN;
+ reset_type = ST_FS8_RESET;
} else {
assert(dispatch_width == 16);
type = ST_FS16;
+ written_type = ST_FS16_WRITTEN;
+ reset_type = ST_FS16_RESET;
}
- emit_shader_time_write(type, shader_start_time, get_timestamp());
-}
-
-void
-fs_visitor::emit_shader_time_write(enum shader_time_shader_type type,
- fs_reg start, fs_reg end)
-{
- /* Choose an index in the buffer and set up tracking information for our
- * printouts.
- */
- int shader_time_index = brw->shader_time.num_entries++;
- assert(shader_time_index <= brw->shader_time.max_entries);
- brw->shader_time.types[shader_time_index] = type;
- if (prog) {
- _mesa_reference_shader_program(ctx,
- &brw->shader_time.programs[shader_time_index],
- prog);
- }
+ fs_reg shader_end_time = get_timestamp();
/* Check that there weren't any timestamp reset events (assuming these
* were the only two timestamp reads that happened).
*/
- fs_reg reset = end;
+ fs_reg reset = shader_end_time;
reset.smear = 2;
fs_inst *test = emit(AND(reg_null_d, reset, fs_reg(1u)));
test->conditional_mod = BRW_CONDITIONAL_Z;
emit(IF(BRW_PREDICATE_NORMAL));
push_force_uncompressed();
+ fs_reg start = shader_start_time;
start.negate = true;
fs_reg diff = fs_reg(this, glsl_type::uint_type);
- emit(ADD(diff, start, end));
+ emit(ADD(diff, start, shader_end_time));
/* If there were no instructions between the two timestamp gets, the diff
* is 2 cycles. Remove that overhead, so I can forget about that when
*/
emit(ADD(diff, diff, fs_reg(-2u)));
+ emit_shader_time_write(type, diff);
+ emit_shader_time_write(written_type, fs_reg(1u));
+ emit(BRW_OPCODE_ELSE);
+ emit_shader_time_write(reset_type, fs_reg(1u));
+ emit(BRW_OPCODE_ENDIF);
+
+ pop_force_uncompressed();
+}
+
+void
+fs_visitor::emit_shader_time_write(enum shader_time_shader_type type,
+ fs_reg value)
+{
+ /* Choose an index in the buffer and set up tracking information for our
+ * printouts.
+ */
+ int shader_time_index = brw->shader_time.num_entries++;
+ assert(shader_time_index <= brw->shader_time.max_entries);
+ brw->shader_time.types[shader_time_index] = type;
+ if (prog) {
+ _mesa_reference_shader_program(ctx,
+ &brw->shader_time.programs[shader_time_index],
+ prog);
+ }
+
int base_mrf = 6;
fs_reg offset_mrf = fs_reg(MRF, base_mrf);
fs_reg time_mrf = fs_reg(MRF, base_mrf + 1);
time_mrf.type = BRW_REGISTER_TYPE_UD;
- emit(MOV(time_mrf, diff));
+ emit(MOV(time_mrf, value));
fs_inst *inst = emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD));
inst->base_mrf = base_mrf;
inst->mlen = 2;
-
- pop_force_uncompressed();
-
- emit(BRW_OPCODE_ENDIF);
}
void
* get stored, rather than in some global gl_shader_program uniform
* store.
*/
-int
-fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
+void
+fs_visitor::setup_uniform_values(ir_variable *ir)
{
- unsigned int offset = 0;
+ int namelen = strlen(ir->name);
- if (type->is_matrix()) {
- const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
- type->vector_elements,
- 1);
-
- for (unsigned int i = 0; i < type->matrix_columns; i++) {
- offset += setup_uniform_values(loc + offset, column);
+ /* The data for our (non-builtin) uniforms is stored in a series of
+ * gl_uniform_driver_storage structs for each subcomponent that
+ * glGetUniformLocation() could name. We know it's been set up in the same
+ * order we'd walk the type, so walk the list of storage and find anything
+ * with our name, or the prefix of a component that starts with our name.
+ */
+ unsigned params_before = c->prog_data.nr_params;
+ for (unsigned u = 0; u < prog->NumUserUniformStorage; u++) {
+ struct gl_uniform_storage *storage = &prog->UniformStorage[u];
+
+ if (strncmp(ir->name, storage->name, namelen) != 0 ||
+ (storage->name[namelen] != 0 &&
+ storage->name[namelen] != '.' &&
+ storage->name[namelen] != '[')) {
+ continue;
}
- return offset;
- }
+ unsigned slots = storage->type->component_slots();
+ if (storage->array_elements)
+ slots *= storage->array_elements;
- switch (type->base_type) {
- case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_INT:
- case GLSL_TYPE_BOOL:
- for (unsigned int i = 0; i < type->vector_elements; i++) {
- unsigned int param = c->prog_data.nr_params++;
-
- this->param_index[param] = loc;
- this->param_offset[param] = i;
+ for (unsigned i = 0; i < slots; i++) {
+ c->prog_data.param[c->prog_data.nr_params++] =
+ &storage->storage[i].f;
}
- return 1;
-
- case GLSL_TYPE_STRUCT:
- for (unsigned int i = 0; i < type->length; i++) {
- offset += setup_uniform_values(loc + offset,
- type->fields.structure[i].type);
- }
- return offset;
-
- case GLSL_TYPE_ARRAY:
- for (unsigned int i = 0; i < type->length; i++) {
- offset += setup_uniform_values(loc + offset, type->fields.array);
- }
- return offset;
-
- case GLSL_TYPE_SAMPLER:
- /* The sampler takes up a slot, but we don't use any values from it. */
- return 1;
-
- default:
- assert(!"not reached");
- return 0;
}
+
+ /* Make sure we actually initialized the right amount of stuff here. */
+ assert(params_before + ir->type->component_slots() ==
+ c->prog_data.nr_params);
}
break;
last_swiz = swiz;
- this->param_index[c->prog_data.nr_params] = index;
- this->param_offset[c->prog_data.nr_params] = swiz;
- c->prog_data.nr_params++;
+ c->prog_data.param[c->prog_data.nr_params++] =
+ &fp->Base.Parameters->ParameterValues[index][swiz].f;
}
}
}
return reg;
}
+fs_reg
+fs_visitor::fix_math_operand(fs_reg src)
+{
+ /* Can't do hstride == 0 args on gen6 math, so expand it out. We
+ * might be able to do better by doing execsize = 1 math and then
+ * expanding that result out, but we would need to be careful with
+ * masking.
+ *
+ * The hardware ignores source modifiers (negate and abs) on math
+ * instructions, so we also move to a temp to set those up.
+ */
+ if (intel->gen == 6 && src.file != UNIFORM && src.file != IMM &&
+ !src.abs && !src.negate)
+ return src;
+
+ /* Gen7 relaxes most of the above restrictions, but still can't use IMM
+ * operands to math
+ */
+ if (intel->gen >= 7 && src.file != IMM)
+ return src;
+
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ expanded.type = src.type;
+ emit(BRW_OPCODE_MOV, expanded, src);
+ return expanded;
+}
+
fs_inst *
fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
{
* Gen 6 hardware ignores source modifiers (negate and abs) on math
* instructions, so we also move to a temp to set those up.
*/
- if (intel->gen == 6 && (src.file == UNIFORM ||
- src.abs ||
- src.negate)) {
- fs_reg expanded = fs_reg(this, glsl_type::float_type);
- emit(BRW_OPCODE_MOV, expanded, src);
- src = expanded;
- }
+ if (intel->gen >= 6)
+ src = fix_math_operand(src);
fs_inst *inst = emit(opcode, dst, src);
fs_inst *inst;
switch (opcode) {
- case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
+ if (intel->gen >= 7 && dispatch_width == 16)
+ fail("16-wide INTDIV unsupported\n");
+ break;
+ case SHADER_OPCODE_POW:
break;
default:
assert(!"not reached: unsupported binary math opcode.");
return NULL;
}
- if (intel->gen >= 7) {
- inst = emit(opcode, dst, src0, src1);
- } else if (intel->gen == 6) {
- /* Can't do hstride == 0 args to gen6 math, so expand it out.
- *
- * The hardware ignores source modifiers (negate and abs) on math
- * instructions, so we also move to a temp to set those up.
- */
- if (src0.file == UNIFORM || src0.abs || src0.negate) {
- fs_reg expanded = fs_reg(this, glsl_type::float_type);
- expanded.type = src0.type;
- emit(BRW_OPCODE_MOV, expanded, src0);
- src0 = expanded;
- }
-
- if (src1.file == UNIFORM || src1.abs || src1.negate) {
- fs_reg expanded = fs_reg(this, glsl_type::float_type);
- expanded.type = src1.type;
- emit(BRW_OPCODE_MOV, expanded, src1);
- src1 = expanded;
- }
+ if (intel->gen >= 6) {
+ src0 = fix_math_operand(src0);
+ src1 = fix_math_operand(src1);
inst = emit(opcode, dst, src0, src1);
} else {
return inst;
}
-/**
- * To be called after the last _mesa_add_state_reference() call, to
- * set up prog_data.param[] for assign_curb_setup() and
- * setup_pull_constants().
- */
-void
-fs_visitor::setup_paramvalues_refs()
-{
- if (dispatch_width != 8)
- return;
-
- /* Set up the pointers to ParamValues now that that array is finalized. */
- for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
- c->prog_data.param[i] =
- (const float *)fp->Base.Parameters->ParameterValues[this->param_index[i]] +
- this->param_offset[i];
- }
-}
-
void
fs_visitor::assign_curb_setup()
{
if (remapped == -1)
continue;
- /* We've already done setup_paramvalues_refs() so no need to worry
- * about param_index and param_offset.
- */
c->prog_data.param[remapped] = c->prog_data.param[i];
}
dst, index, offset);
pull->ir = inst->ir;
pull->annotation = inst->annotation;
- pull->base_mrf = 14;
- pull->mlen = 1;
inst->insert_before(pull);
int reg_to = inst->dst.reg;
int reg_to_offset = inst->dst.reg_offset;
- foreach_list_safe(node, &this->instructions) {
+ foreach_list(node, &this->instructions) {
fs_inst *scan_inst = (fs_inst *)node;
if (scan_inst->dst.file == GRF &&
}
inst->remove();
+
+ /* We don't need to recalculate live intervals inside the loop despite
+ * flagging live_intervals_valid because we only use live intervals for
+ * the interferes test, and we must have had a situation where the
+ * intervals were:
+ *
+ * from to
+ * ^
+ * |
+ * v
+ * ^
+ * |
+ * v
+ *
+ * Some register R that might get coalesced with one of these two could
+ * only be referencing "to", otherwise "from"'s range would have been
+ * longer. R's range could also only start at the end of "to" or later,
+ * otherwise it will conflict with "to" when we try to coalesce "to"
+ * into Rw anyway.
+ */
live_intervals_valid = false;
+
progress = true;
continue;
}
bool has_source_modifiers = (inst->src[0].abs ||
inst->src[0].negate ||
+ inst->src[0].smear != -1 ||
inst->src[0].file == UNIFORM);
/* Found a move of a GRF to a GRF. Let's see if we can coalesce
* into a compute-to-MRF.
*/
- /* SENDs can only write to GRFs, so no compute-to-MRF. */
- if (scan_inst->mlen) {
- break;
- }
-
/* If it's predicated, it (probably) didn't populate all
* the channels. We might be able to rewrite everything
* that writes that reg, but it would require smarter
if (scan_inst->mlen)
break;
- if (intel->gen >= 6) {
+ if (intel->gen == 6) {
/* gen6 math instructions must have the destination be
* GRF, so no compute-to-MRF for them.
*/
break;
}
- /* We don't handle flow control here. Most computation of
+ /* We don't handle control flow here. Most computation of
* values that end up in MRFs are shortly before the MRF
* write anyway.
*/
- if (scan_inst->opcode == BRW_OPCODE_DO ||
- scan_inst->opcode == BRW_OPCODE_WHILE ||
- scan_inst->opcode == BRW_OPCODE_ELSE ||
- scan_inst->opcode == BRW_OPCODE_ENDIF) {
+ if (scan_inst->is_control_flow() && scan_inst->opcode != BRW_OPCODE_IF)
break;
- }
/* You can't read from an MRF, so if someone else reads our
* MRF's source GRF that we wanted to rewrite, that stops us.
foreach_list_safe(node, &this->instructions) {
fs_inst *inst = (fs_inst *)node;
- switch (inst->opcode) {
- case BRW_OPCODE_DO:
- case BRW_OPCODE_WHILE:
- case BRW_OPCODE_IF:
- case BRW_OPCODE_ELSE:
- case BRW_OPCODE_ENDIF:
+ if (inst->is_control_flow()) {
memset(last_mrf_move, 0, sizeof(last_mrf_move));
- continue;
- default:
- break;
}
if (inst->opcode == BRW_OPCODE_MOV &&
return progress;
}
+static void
+clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
+ int first_grf, int grf_len)
+{
+ bool inst_16wide = (dispatch_width > 8 &&
+ !inst->force_uncompressed &&
+ !inst->force_sechalf);
+
+ /* Clear the flag for registers that actually got read (as expected). */
+ for (int i = 0; i < 3; i++) {
+ int grf;
+ if (inst->src[i].file == GRF) {
+ grf = inst->src[i].reg;
+ } else if (inst->src[i].file == FIXED_HW_REG &&
+ inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
+ grf = inst->src[i].fixed_hw_reg.nr;
+ } else {
+ continue;
+ }
+
+ if (grf >= first_grf &&
+ grf < first_grf + grf_len) {
+ deps[grf - first_grf] = false;
+ if (inst_16wide)
+ deps[grf - first_grf + 1] = false;
+ }
+ }
+}
+
+/**
+ * Implements this workaround for the original 965:
+ *
+ * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
+ * check for post destination dependencies on this instruction, software
+ * must ensure that there is no destination hazard for the case of ‘write
+ * followed by a posted write’ shown in the following example.
+ *
+ * 1. mov r3 0
+ * 2. send r3.xy <rest of send instruction>
+ * 3. mov r2 r3
+ *
+ * Due to no post-destination dependency check on the ‘send’, the above
+ * code sequence could have two instructions (1 and 2) in flight at the
+ * same time that both consider ‘r3’ as the target of their final writes.
+ */
+void
+fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
+{
+ int write_len = inst->regs_written() * dispatch_width / 8;
+ int first_write_grf = inst->dst.reg;
+ bool needs_dep[BRW_MAX_MRF];
+ assert(write_len < (int)sizeof(needs_dep) - 1);
+
+ memset(needs_dep, false, sizeof(needs_dep));
+ memset(needs_dep, true, write_len);
+
+ clear_deps_for_inst_src(inst, dispatch_width,
+ needs_dep, first_write_grf, write_len);
+
+ /* Walk backwards looking for writes to registers we're writing which
+ * aren't read since being written. If we hit the start of the program,
+ * we assume that there are no outstanding dependencies on entry to the
+ * program.
+ */
+ for (fs_inst *scan_inst = (fs_inst *)inst->prev;
+ scan_inst != NULL;
+ scan_inst = (fs_inst *)scan_inst->prev) {
+
+ /* If we hit control flow, assume that there *are* outstanding
+ * dependencies, and force their cleanup before our instruction.
+ */
+ if (scan_inst->is_control_flow()) {
+ for (int i = 0; i < write_len; i++) {
+ if (needs_dep[i]) {
+ inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
+ }
+ }
+ }
+
+ bool scan_inst_16wide = (dispatch_width > 8 &&
+ !scan_inst->force_uncompressed &&
+ !scan_inst->force_sechalf);
+
+ /* We insert our reads as late as possible on the assumption that any
+ * instruction but a MOV that might have left us an outstanding
+ * dependency has more latency than a MOV.
+ */
+ if (scan_inst->dst.file == GRF &&
+ scan_inst->dst.reg >= first_write_grf &&
+ scan_inst->dst.reg < first_write_grf + write_len &&
+ needs_dep[scan_inst->dst.reg - first_write_grf]) {
+ inst->insert_before(DEP_RESOLVE_MOV(scan_inst->dst.reg));
+ needs_dep[scan_inst->dst.reg - first_write_grf] = false;
+ if (scan_inst_16wide)
+ needs_dep[scan_inst->dst.reg - first_write_grf + 1] = false;
+ }
+
+ /* Clear the flag for registers that actually got read (as expected). */
+ clear_deps_for_inst_src(scan_inst, dispatch_width,
+ needs_dep, first_write_grf, write_len);
+
+ /* Continue the loop only if we haven't resolved all the dependencies */
+ int i;
+ for (i = 0; i < write_len; i++) {
+ if (needs_dep[i])
+ break;
+ }
+ if (i == write_len)
+ return;
+ }
+}
+
+/**
+ * Implements this workaround for the original 965:
+ *
+ * "[DevBW, DevCL] Errata: A destination register from a send can not be
+ * used as a destination register until after it has been sourced by an
+ * instruction with a different destination register.
+ */
+void
+fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst *inst)
+{
+ int write_len = inst->regs_written() * dispatch_width / 8;
+ int first_write_grf = inst->dst.reg;
+ bool needs_dep[BRW_MAX_MRF];
+ assert(write_len < (int)sizeof(needs_dep) - 1);
+
+ memset(needs_dep, false, sizeof(needs_dep));
+ memset(needs_dep, true, write_len);
+ /* Walk forwards looking for writes to registers we're writing which aren't
+ * read before being written.
+ */
+ for (fs_inst *scan_inst = (fs_inst *)inst->next;
+ !scan_inst->is_tail_sentinel();
+ scan_inst = (fs_inst *)scan_inst->next) {
+ /* If we hit control flow, force resolve all remaining dependencies. */
+ if (scan_inst->is_control_flow()) {
+ for (int i = 0; i < write_len; i++) {
+ if (needs_dep[i])
+ scan_inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
+ }
+ }
+
+ /* Clear the flag for registers that actually got read (as expected). */
+ clear_deps_for_inst_src(scan_inst, dispatch_width,
+ needs_dep, first_write_grf, write_len);
+
+ /* We insert our reads as late as possible since they're reading the
+ * result of a SEND, which has massive latency.
+ */
+ if (scan_inst->dst.file == GRF &&
+ scan_inst->dst.reg >= first_write_grf &&
+ scan_inst->dst.reg < first_write_grf + write_len &&
+ needs_dep[scan_inst->dst.reg - first_write_grf]) {
+ scan_inst->insert_before(DEP_RESOLVE_MOV(scan_inst->dst.reg));
+ needs_dep[scan_inst->dst.reg - first_write_grf] = false;
+ }
+
+ /* Continue the loop only if we haven't resolved all the dependencies */
+ int i;
+ for (i = 0; i < write_len; i++) {
+ if (needs_dep[i])
+ break;
+ }
+ if (i == write_len)
+ return;
+ }
+
+ /* If we hit the end of the program, resolve all remaining dependencies out
+ * of paranoia.
+ */
+ fs_inst *last_inst = (fs_inst *)this->instructions.get_tail();
+ assert(last_inst->eot);
+ for (int i = 0; i < write_len; i++) {
+ if (needs_dep[i])
+ last_inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
+ }
+}
+
+void
+fs_visitor::insert_gen4_send_dependency_workarounds()
+{
+ if (intel->gen != 4 || intel->is_g4x)
+ return;
+
+ /* Note that we're done with register allocation, so GRF fs_regs always
+ * have a .reg_offset of 0.
+ */
+
+ foreach_list_safe(node, &this->instructions) {
+ fs_inst *inst = (fs_inst *)node;
+
+ if (inst->mlen != 0 && inst->dst.file == GRF) {
+ insert_gen4_pre_send_dependency_workarounds(inst);
+ insert_gen4_post_send_dependency_workarounds(inst);
+ }
+ }
+}
+
+/**
+ * Turns the generic expression-style uniform pull constant load instruction
+ * into a hardware-specific series of instructions for loading a pull
+ * constant.
+ *
+ * The expression style allows the CSE pass before this to optimize out
+ * repeated loads from the same offset, and gives the pre-register-allocation
+ * scheduling full flexibility, while the conversion to native instructions
+ * allows the post-register-allocation scheduler the best information
+ * possible.
+ */
+void
+fs_visitor::lower_uniform_pull_constant_loads()
+{
+ foreach_list(node, &this->instructions) {
+ fs_inst *inst = (fs_inst *)node;
+
+ if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
+ continue;
+
+ if (intel->gen >= 7) {
+ fs_reg const_offset_reg = inst->src[1];
+ assert(const_offset_reg.file == IMM &&
+ const_offset_reg.type == BRW_REGISTER_TYPE_UD);
+ const_offset_reg.imm.u /= 16;
+ fs_reg payload = fs_reg(this, glsl_type::uint_type);
+ struct brw_reg g0 = retype(brw_vec8_grf(0, 0),
+ BRW_REGISTER_TYPE_UD);
+
+ fs_inst *setup1 = MOV(payload, fs_reg(g0));
+ setup1->force_writemask_all = true;
+ /* We don't need the second half of this vgrf to be filled with g1
+ * in the 16-wide case, but if we use force_uncompressed then live
+ * variable analysis won't consider this a def!
+ */
+
+ fs_inst *setup2 = new(mem_ctx) fs_inst(FS_OPCODE_SET_GLOBAL_OFFSET,
+ payload, payload,
+ const_offset_reg);
+
+ setup1->ir = inst->ir;
+ setup1->annotation = inst->annotation;
+ inst->insert_before(setup1);
+ setup2->ir = inst->ir;
+ setup2->annotation = inst->annotation;
+ inst->insert_before(setup2);
+ inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7;
+ inst->src[1] = payload;
+ } else {
+ /* Before register allocation, we didn't tell the scheduler about the
+ * MRF we use. We know it's safe to use this MRF because nothing
+ * else does except for register spill/unspill, which generates and
+ * uses its MRF within a single IR instruction.
+ */
+ inst->base_mrf = 14;
+ inst->mlen = 1;
+ }
+ }
+}
+
void
fs_visitor::dump_instruction(fs_inst *inst)
{
opcode_descs[inst->opcode].name) {
printf("%s", opcode_descs[inst->opcode].name);
} else {
- printf("op%d", inst->opcode);
+ switch (inst->opcode) {
+ case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
+ printf("uniform_pull_const");
+ break;
+ case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
+ printf("uniform_pull_const_gen7");
+ break;
+ case FS_OPCODE_SET_GLOBAL_OFFSET:
+ printf("set_global_offset");
+ break;
+ default:
+ printf("op%d", inst->opcode);
+ break;
+ }
}
if (inst->saturate)
printf(".sat");
case BAD_FILE:
printf("(null)");
break;
+ case IMM:
+ switch (inst->src[i].type) {
+ case BRW_REGISTER_TYPE_F:
+ printf("%ff", inst->src[i].imm.f);
+ break;
+ case BRW_REGISTER_TYPE_D:
+ printf("%dd", inst->src[i].imm.i);
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ printf("%uu", inst->src[i].imm.u);
+ break;
+ default:
+ printf("???");
+ break;
+ }
+ break;
default:
printf("???");
break;
bool
fs_visitor::run()
{
+ sanity_param_count = fp->Base.Parameters->NumParameters;
uint32_t orig_nr_params = c->prog_data.nr_params;
if (intel->gen >= 6)
else
emit_interpolation_setup_gen6();
+ /* We handle discards by keeping track of the still-live pixels in f0.1.
+ * Initialize it with the dispatched pixels.
+ */
+ if (fp->UsesKill) {
+ fs_inst *discard_init = emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
+ discard_init->flag_subreg = 1;
+ }
+
/* Generate FS IR for main(). (the visitor only descends into
* functions called "main").
*/
split_virtual_grfs();
- setup_paramvalues_refs();
move_uniform_array_access_to_pull_constants();
setup_pull_constants();
remove_dead_constants();
- schedule_instructions();
+ schedule_instructions(false);
+
+ lower_uniform_pull_constant_loads();
assign_curb_setup();
assign_urb_setup();
assert(force_uncompressed_stack == 0);
assert(force_sechalf_stack == 0);
+ /* This must come after all optimization and register allocation, since
+ * it inserts dead code that happens to have side effects, and it does
+ * so based on the actual physical registers in use.
+ */
+ insert_gen4_send_dependency_workarounds();
+
if (failed)
return false;
+ schedule_instructions(true);
+
if (dispatch_width == 8) {
c->prog_data.reg_blocks = brw_register_blocks(grf_used);
} else {
(void) orig_nr_params;
}
+ /* If any state parameters were appended, then ParameterValues could have
+ * been realloced, in which case the driver uniform storage set up by
+ * _mesa_associate_uniform_storage() would point to freed memory. Make
+ * sure that didn't happen.
+ */
+ assert(sanity_param_count == fp->Base.Parameters->NumParameters);
+
return !failed;
}
exec_list *simd16_instructions = NULL;
fs_visitor v2(brw, c, prog, fp, 16);
- if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) {
+ bool no16 = INTEL_DEBUG & DEBUG_NO16;
+ if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0 && likely(!no16)) {
v2.import_uniforms(&v);
if (!v2.run()) {
perf_debug("16-wide shader failed to compile, falling back to "
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