#include "brw_shader.h"
#include "brw_ir_fs.h"
#include "brw_fs_builder.h"
-
-extern "C" {
-
-#include <sys/types.h>
-
-#include "main/macros.h"
-#include "main/shaderobj.h"
-#include "main/uniforms.h"
-#include "program/prog_parameter.h"
-#include "program/prog_print.h"
-#include "program/prog_optimize.h"
-#include "util/register_allocate.h"
-#include "program/hash_table.h"
-#include "brw_context.h"
-#include "brw_eu.h"
-#include "brw_wm.h"
-#include "intel_asm_annotation.h"
-}
-#include "glsl/glsl_types.h"
#include "glsl/ir.h"
#include "glsl/nir/nir.h"
-#include "program/sampler.h"
struct bblock_t;
namespace {
class fs_live_variables;
}
+struct brw_gs_compile;
+
+static inline fs_reg
+offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
+{
+ switch (reg.file) {
+ case BAD_FILE:
+ break;
+ case ARF:
+ case FIXED_GRF:
+ case MRF:
+ case VGRF:
+ case ATTR:
+ return byte_offset(reg,
+ delta * reg.component_size(bld.dispatch_width()));
+ case UNIFORM:
+ reg.reg_offset += delta;
+ break;
+ case IMM:
+ assert(delta == 0);
+ }
+ return reg;
+}
+
/**
* The fragment shader front-end.
*
class fs_visitor : public backend_shader
{
public:
- fs_visitor(struct brw_context *brw,
+ fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
- gl_shader_stage stage,
const void *key,
struct brw_stage_prog_data *prog_data,
- struct gl_shader_program *shader_prog,
struct gl_program *prog,
+ const nir_shader *shader,
unsigned dispatch_width,
int shader_time_index);
-
+ fs_visitor(const struct brw_compiler *compiler, void *log_data,
+ void *mem_ctx,
+ struct brw_gs_compile *gs_compile,
+ struct brw_gs_prog_data *prog_data,
+ const nir_shader *shader,
+ int shader_time_index);
+ void init();
~fs_visitor();
fs_reg vgrf(const glsl_type *const type);
void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
void compute_clip_distance(gl_clip_plane *clip_planes);
- uint32_t gather_channel(int orig_chan, uint32_t sampler);
- void swizzle_result(ir_texture_opcode op, int dest_components,
- fs_reg orig_val, uint32_t sampler);
-
- int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
fs_inst *end,
const fs_reg ®);
bool run_fs(bool do_rep_send);
bool run_vs(gl_clip_plane *clip_planes);
+ bool run_gs();
bool run_cs();
void optimize();
void allocate_registers();
- void assign_binding_table_offsets();
void setup_payload_gen4();
void setup_payload_gen6();
void setup_vs_payload();
+ void setup_gs_payload();
void setup_cs_payload();
void fixup_3src_null_dest();
void assign_curb_setup();
void calculate_urb_setup();
void assign_urb_setup();
+ void convert_attr_sources_to_hw_regs(fs_inst *inst);
void assign_vs_urb_setup();
+ void assign_gs_urb_setup();
bool assign_regs(bool allow_spilling);
void assign_regs_trivial();
+ void calculate_payload_ranges(int payload_node_count,
+ int *payload_last_use_ip);
void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
int first_payload_node);
int choose_spill_reg(struct ra_graph *g);
void spill_reg(int spill_reg);
void split_virtual_grfs();
bool compact_virtual_grfs();
- void move_uniform_array_access_to_pull_constants();
void assign_constant_locations();
void demote_pull_constants();
void invalidate_live_intervals();
void calculate_live_intervals();
void calculate_register_pressure();
+ void validate();
bool opt_algebraic();
bool opt_redundant_discard_jumps();
bool opt_cse();
void no16(const char *msg);
void lower_uniform_pull_constant_loads();
bool lower_load_payload();
+ bool lower_logical_sends();
bool lower_integer_multiplication();
+ bool lower_simd_width();
bool opt_combine_constants();
void emit_dummy_fs();
fs_reg *emit_frontfacing_interpolation();
fs_reg *emit_samplepos_setup();
fs_reg *emit_sampleid_setup();
- void emit_general_interpolation(fs_reg attr, const char *name,
+ void emit_general_interpolation(fs_reg *attr, const char *name,
const glsl_type *type,
glsl_interp_qualifier interpolation_mode,
- int location, bool mod_centroid,
+ int *location, bool mod_centroid,
bool mod_sample);
fs_reg *emit_vs_system_value(int location);
void emit_interpolation_setup_gen4();
void emit_interpolation_setup_gen6();
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
- fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
- bool is_rect, uint32_t sampler, int texunit);
- fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int coord_components,
- fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int grad_components,
- uint32_t sampler);
- fs_inst *emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int vector_elements,
- fs_reg shadow_c, fs_reg lod,
- uint32_t sampler);
- fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int coord_components,
- fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int grad_components,
- fs_reg sample_index, uint32_t sampler,
- bool has_offset);
- fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int coord_components,
- fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int grad_components,
- fs_reg sample_index, fs_reg mcs, fs_reg sampler,
- fs_reg offset_value);
void emit_texture(ir_texture_opcode op,
const glsl_type *dest_type,
fs_reg coordinate, int components,
fs_reg mcs,
int gather_component,
bool is_cube_array,
- bool is_rect,
+ uint32_t surface,
+ fs_reg surface_reg,
uint32_t sampler,
- fs_reg sampler_reg,
- int texunit);
- fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
+ fs_reg sampler_reg);
+ fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
+ const fs_reg &sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
- void resolve_source_modifiers(fs_reg *src);
+ fs_reg resolve_source_modifiers(const fs_reg &src);
void emit_discard_jump();
- bool try_replace_with_sel();
bool opt_peephole_sel();
bool opt_peephole_predicated_break();
bool opt_saturate_propagation();
uint32_t spill_offset, int count);
void emit_nir_code();
- void nir_setup_inputs(nir_shader *shader);
- void nir_setup_outputs(nir_shader *shader);
- void nir_setup_uniforms(nir_shader *shader);
- void nir_setup_uniform(nir_variable *var);
- void nir_setup_builtin_uniform(nir_variable *var);
- void nir_emit_system_values(nir_shader *shader);
+ void nir_setup_inputs();
+ void nir_setup_single_output_varying(fs_reg *reg, const glsl_type *type,
+ unsigned *location);
+ void nir_setup_outputs();
+ void nir_setup_uniforms();
+ void nir_emit_system_values();
void nir_emit_impl(nir_function_impl *impl);
void nir_emit_cf_list(exec_list *list);
void nir_emit_if(nir_if *if_stmt);
void nir_emit_block(nir_block *block);
void nir_emit_instr(nir_instr *instr);
void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
+ void nir_emit_load_const(const brw::fs_builder &bld,
+ nir_load_const_instr *instr);
+ void nir_emit_undef(const brw::fs_builder &bld,
+ nir_ssa_undef_instr *instr);
+ void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
+ nir_intrinsic_instr *instr);
+ void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
+ nir_intrinsic_instr *instr);
+ void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
+ nir_intrinsic_instr *instr);
+ void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
+ nir_intrinsic_instr *instr);
void nir_emit_intrinsic(const brw::fs_builder &bld,
nir_intrinsic_instr *instr);
+ void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
+ int op, nir_intrinsic_instr *instr);
+ void nir_emit_shared_atomic(const brw::fs_builder &bld,
+ int op, nir_intrinsic_instr *instr);
void nir_emit_texture(const brw::fs_builder &bld,
nir_tex_instr *instr);
void nir_emit_jump(const brw::fs_builder &bld,
nir_jump_instr *instr);
fs_reg get_nir_src(nir_src src);
fs_reg get_nir_dest(nir_dest dest);
+ fs_reg get_nir_image_deref(const nir_deref_var *deref);
void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
unsigned wr_mask);
bool optimize_frontfacing_ternary(nir_alu_instr *instr,
const fs_reg &result);
- void setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
- unsigned exec_size, bool use_2nd_half);
void emit_alpha_test();
fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
fs_reg color1, fs_reg color2,
- fs_reg src0_alpha, unsigned components,
- unsigned exec_size, bool use_2nd_half = false);
+ fs_reg src0_alpha, unsigned components);
void emit_fb_writes();
- void emit_urb_writes(gl_clip_plane *clip_planes);
+ void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
+ void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
+ unsigned stream_id);
+ void emit_gs_control_data_bits(const fs_reg &vertex_count);
+ void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
+ void emit_gs_vertex(const nir_src &vertex_count_nir_src,
+ unsigned stream_id);
+ void emit_gs_thread_end();
+ void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
+ unsigned base_offset, const nir_src &offset_src,
+ unsigned num_components);
void emit_cs_terminate();
+ fs_reg *emit_cs_local_invocation_id_setup();
+ fs_reg *emit_cs_work_group_id_setup();
void emit_barrier();
int shader_time_subindex,
fs_reg value);
- void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
- fs_reg dst, fs_reg offset, fs_reg src0,
- fs_reg src1);
-
- void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
- fs_reg offset);
-
fs_reg get_timestamp(const brw::fs_builder &bld);
struct brw_reg interp_reg(int location, int channel);
+
int implied_mrf_writes(fs_inst *inst);
virtual void dump_instructions();
const void *const key;
const struct brw_sampler_prog_key_data *key_tex;
+ struct brw_gs_compile *gs_compile;
+
struct brw_stage_prog_data *prog_data;
- unsigned int sanity_param_count;
+ struct gl_program *prog;
int *param_size;
/** Number of uniform variable components visited. */
unsigned uniforms;
- /** Total number of direct uniforms we can get from NIR */
- unsigned num_direct_uniforms;
-
/** Byte-offset for the next available spot in the scratch space buffer. */
unsigned last_scratch;
int *push_constant_loc;
fs_reg frag_depth;
+ fs_reg frag_stencil;
fs_reg sample_mask;
fs_reg outputs[VARYING_SLOT_MAX];
unsigned output_components[VARYING_SLOT_MAX];
unsigned max_grf;
fs_reg *nir_locals;
- fs_reg *nir_globals;
+ fs_reg *nir_ssa_values;
fs_reg nir_inputs;
fs_reg nir_outputs;
fs_reg *nir_system_values;
fs_reg result;
/** Register numbers for thread payload fields. */
- struct {
+ struct thread_payload {
uint8_t source_depth_reg;
uint8_t source_w_reg;
uint8_t aa_dest_stencil_reg;
uint8_t sample_pos_reg;
uint8_t sample_mask_in_reg;
uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
+ uint8_t local_invocation_id_reg;
/** The number of thread payload registers the hardware will supply. */
uint8_t num_regs;
fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
fs_reg shader_start_time;
fs_reg userplane[MAX_CLIP_PLANES];
+ fs_reg final_gs_vertex_count;
+ fs_reg control_data_bits;
unsigned grf_used;
bool spilled_any_registers;
void *mem_ctx,
const void *key,
struct brw_stage_prog_data *prog_data,
- struct gl_program *fp,
unsigned promoted_constants,
bool runtime_check_aads_emit,
const char *stage_abbrev);
struct brw_reg implied_header,
GLuint nr);
void generate_fb_write(fs_inst *inst, struct brw_reg payload);
+ void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
void generate_urb_write(fs_inst *inst, struct brw_reg payload);
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
+ void generate_stencil_ref_packing(fs_inst *inst, struct brw_reg dst,
+ struct brw_reg src);
void generate_barrier(fs_inst *inst, struct brw_reg src);
void generate_blorp_fb_write(fs_inst *inst);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+ struct brw_reg surface_index,
struct brw_reg sampler_index);
+ void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
+ struct brw_reg src,
+ struct brw_reg surf_index);
void generate_math_gen6(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg msg_data,
unsigned msg_type);
- void generate_set_omask(fs_inst *inst,
- struct brw_reg dst,
- struct brw_reg sample_mask);
-
void generate_set_sample_id(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg offset,
struct brw_reg value);
+ void generate_mov_indirect(fs_inst *inst,
+ struct brw_reg dst,
+ struct brw_reg reg,
+ struct brw_reg indirect_byte_offset);
+
bool patch_discard_jumps_to_fb_writes();
const struct brw_compiler *compiler;
const void * const key;
struct brw_stage_prog_data * const prog_data;
- const struct gl_program *prog;
-
unsigned dispatch_width; /**< 8 or 16 */
exec_list discard_halt_patches;
bool brw_do_channel_expressions(struct exec_list *instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
-void brw_setup_tex_for_precompile(struct brw_context *brw,
- struct brw_sampler_prog_key_data *tex,
- struct gl_program *prog);
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