* sizeof(float))
/** \} */
-
-/**
- * Compute masks to determine how much of draw_x and draw_y should be
- * performed using the fine adjustment of "depth coordinate offset X/Y"
- * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for
- * details.
- */
-void
-gen6_blorp_compute_tile_masks(const brw_blorp_params *params,
- uint32_t *tile_mask_x, uint32_t *tile_mask_y)
-{
- uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y;
- intel_region_get_tile_masks(params->depth.mt->region,
- &depth_mask_x, &depth_mask_y, false);
- intel_region_get_tile_masks(params->depth.mt->hiz_mt->region,
- &hiz_mask_x, &hiz_mask_y, false);
-
- /* Each HiZ row represents 2 rows of pixels */
- hiz_mask_y = hiz_mask_y << 1 | 1;
-
- *tile_mask_x = depth_mask_x | hiz_mask_x;
- *tile_mask_y = depth_mask_y | hiz_mask_y;
-}
-
-
void
gen6_blorp_emit_batch_head(struct brw_context *brw,
const brw_blorp_params *params)
{
struct gl_context *ctx = &brw->intel.ctx;
- struct intel_context *intel = &brw->intel;
/* To ensure that the batch contains only the resolve, flush the batch
* before beginning and after finishing emitting the resolve packets.
- *
- * Ideally, we would not need to flush for the resolve op. But, I suspect
- * that it's unsafe for CMD_PIPELINE_SELECT to occur multiple times in
- * a single batch, and there is no safe way to ensure that other than by
- * fencing the resolve with flushes. Ideally, we would just detect if
- * a batch is in progress and do the right thing, but that would require
- * the ability to *safely* access brw_context::state::dirty::brw
- * outside of the brw_upload_state() codepath.
*/
intel_flush(ctx);
-
- /* CMD_PIPELINE_SELECT
- *
- * Select the 3D pipeline, as opposed to the media pipeline.
- */
- {
- BEGIN_BATCH(1);
- OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16);
- ADVANCE_BATCH();
- }
}
blend->blend1.post_blend_clamp_enable = 1;
blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
- blend->blend1.write_disable_r = false;
- blend->blend1.write_disable_g = false;
- blend->blend1.write_disable_b = false;
- blend->blend1.write_disable_a = false;
+ blend->blend1.write_disable_r = params->color_write_disable[0];
+ blend->blend1.write_disable_g = params->color_write_disable[1];
+ blend->blend1.write_disable_b = params->color_write_disable[2];
+ blend->blend1.write_disable_a = params->color_write_disable[3];
+
+ /* When blitting from an XRGB source to a ARGB destination, we need to
+ * interpret the missing channel as 1.0. Blending can do that for us:
+ * we simply use the RGB values from the fragment shader ("source RGB"),
+ * but smash the alpha channel to 1.
+ */
+ if (params->src.mt &&
+ _mesa_get_format_bits(params->dst.mt->format, GL_ALPHA_BITS) > 0 &&
+ _mesa_get_format_bits(params->src.mt->format, GL_ALPHA_BITS) == 0) {
+ blend->blend0.blend_enable = 1;
+ blend->blend0.ia_blend_enable = 1;
+
+ blend->blend0.blend_func = BRW_BLENDFUNCTION_ADD;
+ blend->blend0.ia_blend_func = BRW_BLENDFUNCTION_ADD;
+
+ blend->blend0.source_blend_factor = BRW_BLENDFACTOR_SRC_COLOR;
+ blend->blend0.dest_blend_factor = BRW_BLENDFACTOR_ZERO;
+ blend->blend0.ia_source_blend_factor = BRW_BLENDFACTOR_ONE;
+ blend->blend0.ia_dest_blend_factor = BRW_BLENDFACTOR_ZERO;
+ }
return cc_blend_state_offset;
}
uint32_t tiling = surface->map_stencil_as_y_tiled
? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y
: brw_get_surface_tiling_bits(region->tiling);
- uint32_t pitch_bytes = region->pitch * region->cpp;
+ uint32_t pitch_bytes = region->pitch;
if (surface->map_stencil_as_y_tiled)
pitch_bytes *= 2;
surf[3] = (tiling |
intel_emit_post_sync_nonzero_flush(intel);
}
+ /* Disable the push constant buffers. */
+ BEGIN_BATCH(5);
+ OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(0);
{
struct intel_context *intel = &brw->intel;
+ /* Disable all the constant buffers. */
+ BEGIN_BATCH(5);
+ OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
OUT_BATCH(0);
assert(0);
break;
}
- dw4 |= GEN6_WM_STATISTICS_ENABLE;
dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
ADVANCE_BATCH();
}
+static void
+gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
+ const brw_blorp_params *params)
+{
+ struct intel_context *intel = &brw->intel;
+
+ /* Disable the push constant buffers. */
+ BEGIN_BATCH(5);
+ OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
/**
* 3DSTATE_BINDING_TABLE_POINTERS
const brw_blorp_params *params)
{
struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
uint32_t draw_x = params->depth.x_offset;
uint32_t draw_y = params->depth.y_offset;
uint32_t tile_mask_x, tile_mask_y;
- gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
+ brw_get_depthstencil_tile_masks(params->depth.mt,
+ params->depth.level,
+ params->depth.layer,
+ NULL,
+ &tile_mask_x, &tile_mask_y);
/* 3DSTATE_DEPTH_BUFFER */
{
* tile_x and tile_y to 0. This is a temporary workaround until we come
* up with a better solution.
*/
+ WARN_ONCE((tile_x & 7) || (tile_y & 7),
+ "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
+ "Truncating offset, bad rendering may occur.\n");
tile_x &= ~7;
tile_y &= ~7;
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- uint32_t pitch_bytes =
- params->depth.mt->region->pitch * params->depth.mt->region->cpp;
- OUT_BATCH((pitch_bytes - 1) |
+ OUT_BATCH((params->depth.mt->region->pitch - 1) |
params->depth_format << 18 |
1 << 21 | /* separate stencil enable */
1 << 22 | /* hiz enable */
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
- OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
+ OUT_BATCH(hiz_region->pitch - 1);
OUT_RELOC(hiz_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
hiz_offset);
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
gen6_blorp_emit_batch_head(brw, params);
gen6_emit_3dstate_multisample(brw, params->num_samples);
- gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false);
+ gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
gen6_blorp_emit_state_base_address(brw, params);
gen6_blorp_emit_vertices(brw, params);
gen6_blorp_emit_urb_config(brw, params);
depthstencil_offset, cc_state_offset);
if (params->use_wm_prog) {
uint32_t wm_surf_offset_renderbuffer;
- uint32_t wm_surf_offset_texture;
+ uint32_t wm_surf_offset_texture = 0;
uint32_t sampler_offset;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
wm_surf_offset_renderbuffer =
gen6_blorp_emit_surface_state(brw, params, ¶ms->dst,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
- wm_surf_offset_texture =
- gen6_blorp_emit_surface_state(brw, params, ¶ms->src,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ if (params->src.mt) {
+ wm_surf_offset_texture =
+ gen6_blorp_emit_surface_state(brw, params, ¶ms->src,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+ }
wm_bind_bo_offset =
gen6_blorp_emit_binding_table(brw, params,
wm_surf_offset_renderbuffer,
gen6_blorp_emit_sf_config(brw, params);
if (params->use_wm_prog)
gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
+ else
+ gen6_blorp_emit_constant_ps_disable(brw, params);
gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
if (params->use_wm_prog)
gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset);
gen6_blorp_emit_clear_params(brw, params);
gen6_blorp_emit_drawing_rectangle(brw, params);
gen6_blorp_emit_primitive(brw, params);
-
- /* See comments above at first invocation of intel_flush() in
- * gen6_blorp_emit_batch_head().
- */
- intel_flush(ctx);
-
- /* Be safe. */
- brw->state.dirty.brw = ~0;
- brw->state.dirty.cache = ~0;
}
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