* found in the LICENSE file.
*/
-#ifdef GBM_TEGRA
+#ifdef DRV_TEGRA
+#include <stdio.h>
#include <string.h>
+#include <sys/mman.h>
#include <xf86drm.h>
#include <tegra_drm.h>
-#include "gbm_priv.h"
+#include "drv_priv.h"
#include "helpers.h"
+#include "util.h"
-int gbm_tegra_bo_create(struct gbm_bo *bo, uint32_t width, uint32_t height, uint32_t format, uint32_t flags)
+/*
+ * GOB (Group Of Bytes) is the basic unit of the blocklinear layout.
+ * GOBs are arranged to blocks, where the height of the block (measured
+ * in GOBs) is configurable.
+ */
+#define NV_BLOCKLINEAR_GOB_HEIGHT 8
+#define NV_BLOCKLINEAR_GOB_WIDTH 64
+#define NV_DEFAULT_BLOCK_HEIGHT_LOG2 4
+#define NV_PREFERRED_PAGE_SIZE (128 * 1024)
+
+enum nv_mem_kind
+{
+ NV_MEM_KIND_PITCH = 0,
+ NV_MEM_KIND_C32_2CRA = 0xdb,
+ NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
+};
+
+static struct supported_combination combos[4] = {
+ {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+ DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
+ {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+ DRV_BO_USE_RENDERING | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
+ {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+ DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
+ {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+ DRV_BO_USE_RENDERING | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
+};
+
+static int compute_block_height_log2(int height)
+{
+ int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
+
+ if (block_height_log2 > 0) {
+ /* Shrink, if a smaller block height could cover the whole
+ * surface height. */
+ int proposed = NV_BLOCKLINEAR_GOB_HEIGHT << (block_height_log2 - 1);
+ while (proposed >= height) {
+ block_height_log2--;
+ if (block_height_log2 == 0)
+ break;
+ proposed /= 2;
+ }
+ }
+ return block_height_log2;
+}
+
+static void compute_layout_blocklinear(int width, int height, int format,
+ enum nv_mem_kind *kind,
+ uint32_t *block_height_log2,
+ uint32_t *stride, uint32_t *size)
+{
+ int pitch = drv_stride_from_format(format, width, 0);
+
+ /* Align to blocklinear blocks. */
+ pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
+
+ /* Compute padded height. */
+ *block_height_log2 = compute_block_height_log2(height);
+ int block_height = 1 << *block_height_log2;
+ int padded_height =
+ ALIGN(height, NV_BLOCKLINEAR_GOB_HEIGHT * block_height);
+
+ int bytes = pitch * padded_height;
+
+ /* Pad the allocation to the preferred page size.
+ * This will reduce the required page table size (see discussion in NV
+ * bug 1321091), and also acts as a WAR for NV bug 1325421.
+ */
+ bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
+
+ *kind = NV_MEM_KIND_C32_2CRA;
+ *stride = pitch;
+ *size = bytes;
+}
+
+static void compute_layout_linear(int width, int height, int format,
+ uint32_t *stride, uint32_t *size)
+{
+ *stride = drv_stride_from_format(format, width, 0);
+ *size = *stride * height;
+}
+
+static int tegra_init(struct driver *drv)
+{
+ drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
+ return drv_add_kms_flags(drv);
+}
+
+static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height,
+ uint32_t format, uint32_t flags)
{
- size_t size = width * height * gbm_bytes_from_format(format);
+ uint32_t size, stride, block_height_log2 = 0;
+ enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
struct drm_tegra_gem_create gem_create;
int ret;
+ if (flags & DRV_BO_USE_RENDERING)
+ compute_layout_blocklinear(width, height, format, &kind,
+ &block_height_log2, &stride, &size);
+ else
+ compute_layout_linear(width, height, format, &stride, &size);
+
memset(&gem_create, 0, sizeof(gem_create));
gem_create.size = size;
gem_create.flags = 0;
- ret = drmIoctl(bo->gbm->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
- if (ret)
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
+ if (ret) {
+ fprintf(stderr, "drv: DRM_IOCTL_TEGRA_GEM_CREATE failed "
+ "(size=%zu)\n", size);
return ret;
+ }
+
+ bo->handles[0].u32 = gem_create.handle;
+ bo->offsets[0] = 0;
+ bo->total_size = bo->sizes[0] = size;
+ bo->strides[0] = stride;
+
+ if (kind != NV_MEM_KIND_PITCH) {
+ struct drm_tegra_gem_set_tiling gem_tile;
+
+ memset(&gem_tile, 0, sizeof(gem_tile));
+ gem_tile.handle = bo->handles[0].u32;
+ gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
+ gem_tile.value = block_height_log2;
+
+ ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING,
+ &gem_tile, sizeof(gem_tile));
+ if (ret < 0) {
+ drv_gem_bo_destroy(bo);
+ return ret;
+ }
- bo->handle.u32 = gem_create.handle;
- bo->size = size;
- bo->stride = width * gbm_bytes_from_format(format);
+ /* Encode blocklinear parameters for EGLImage creation. */
+ bo->tiling = (kind & 0xff) |
+ ((block_height_log2 & 0xf) << 8);
+ bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
+ }
return 0;
}
-struct gbm_driver gbm_driver_tegra =
+static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane)
{
- .name = "tegra",
- .bo_create = gbm_tegra_bo_create,
- .bo_destroy = gbm_gem_bo_destroy,
- .format_list = {
- {GBM_FORMAT_XRGB8888, GBM_BO_USE_SCANOUT | GBM_BO_USE_CURSOR | GBM_BO_USE_RENDERING | GBM_BO_USE_WRITE},
- {GBM_FORMAT_ARGB8888, GBM_BO_USE_SCANOUT | GBM_BO_USE_CURSOR | GBM_BO_USE_RENDERING | GBM_BO_USE_WRITE},
+ int ret;
+ struct drm_tegra_gem_mmap gem_map;
+
+ memset(&gem_map, 0, sizeof(gem_map));
+ gem_map.handle = bo->handles[0].u32;
+
+ ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map,
+ sizeof(gem_map));
+ if (ret < 0) {
+ fprintf(stderr, "drv: DRM_TEGRA_GEM_MMAP failed\n");
+ return MAP_FAILED;
}
+
+ data->length = bo->total_size;
+
+ return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
+ bo->drv->fd, gem_map.offset);
+}
+
+struct backend backend_tegra =
+{
+ .name = "tegra",
+ .init = tegra_init,
+ .bo_create = tegra_bo_create,
+ .bo_destroy = drv_gem_bo_destroy,
+ .bo_map = tegra_bo_map,
};
#endif
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