/*
- * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
-#ifdef GBM_TEGRA
+#ifdef DRV_TEGRA
#include <stdio.h>
#include <string.h>
+#include <sys/mman.h>
#include <xf86drm.h>
#include <tegra_drm.h>
-#include "gbm_priv.h"
+#include "drv_priv.h"
#include "helpers.h"
#include "util.h"
enum nv_mem_kind
{
NV_MEM_KIND_PITCH = 0,
+ NV_MEM_KIND_C32_2CRA = 0xdb,
NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
};
+static struct supported_combination combos[4] = {
+ {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+ {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+ {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+ {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+ BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+};
+
static int compute_block_height_log2(int height)
{
int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
uint32_t *block_height_log2,
uint32_t *stride, uint32_t *size)
{
- int pitch = gbm_stride_from_format(format, width);
+ int pitch = drv_stride_from_format(format, width, 0);
/* Align to blocklinear blocks. */
pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
*/
bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
- *kind = NV_MEM_KIND_GENERIC_16Bx2;
+ *kind = NV_MEM_KIND_C32_2CRA;
*stride = pitch;
*size = bytes;
}
static void compute_layout_linear(int width, int height, int format,
uint32_t *stride, uint32_t *size)
{
- *stride = gbm_stride_from_format(format, width);
+ *stride = ALIGN(drv_stride_from_format(format, width, 0), 64);
*size = *stride * height;
}
-static int gbm_tegra_bo_create(struct gbm_bo *bo, uint32_t width,
- uint32_t height, uint32_t format, uint32_t flags)
+static int tegra_init(struct driver *drv)
+{
+ drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
+ return drv_add_kms_flags(drv);
+}
+
+static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height,
+ uint32_t format, uint32_t flags)
{
uint32_t size, stride, block_height_log2 = 0;
enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
struct drm_tegra_gem_create gem_create;
int ret;
- if (flags & GBM_BO_USE_RENDERING)
+ if (flags & BO_USE_RENDERING)
compute_layout_blocklinear(width, height, format, &kind,
&block_height_log2, &stride, &size);
else
gem_create.size = size;
gem_create.flags = 0;
- ret = drmIoctl(bo->gbm->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
if (ret) {
- fprintf(stderr, "minigbm: DRM_IOCTL_TEGRA_GEM_CREATE failed "
+ fprintf(stderr, "drv: DRM_IOCTL_TEGRA_GEM_CREATE failed "
"(size=%zu)\n", size);
return ret;
}
bo->handles[0].u32 = gem_create.handle;
bo->offsets[0] = 0;
- bo->sizes[0] = size;
+ bo->total_size = bo->sizes[0] = size;
bo->strides[0] = stride;
if (kind != NV_MEM_KIND_PITCH) {
gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
gem_tile.value = block_height_log2;
- ret = drmCommandWriteRead(bo->gbm->fd, DRM_TEGRA_GEM_SET_TILING,
+ ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING,
&gem_tile, sizeof(gem_tile));
if (ret < 0) {
- gbm_gem_bo_destroy(bo);
+ drv_gem_bo_destroy(bo);
return ret;
}
/* Encode blocklinear parameters for EGLImage creation. */
-
- /* XXX Bringup hack: If the highest order bit is set in
- * EGL_DMA_BUF_PLANE0_PITCH_EXT, Nvidia driver treats it as
- * a hint that the buffer is tiled, and the remaining bits in
- * the pitch attribute are treated as vendor specific tiling
- * arguments. Using this hack means that we don't need to add
- * a new FOURCC format, or EGL_DMA_BUF_PLANE0_TILING_EXT
- * attribute to the dma-buf import extension.
- */
- bo->tiling = (1 << 31) |
- (kind & 0xff) |
+ bo->tiling = (kind & 0xff) |
((block_height_log2 & 0xf) << 8);
+ bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
}
return 0;
}
-const struct gbm_driver gbm_driver_tegra =
+static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane)
{
- .name = "tegra",
- .bo_create = gbm_tegra_bo_create,
- .bo_destroy = gbm_gem_bo_destroy,
- .format_list = {
- /* Linear support */
- {GBM_FORMAT_XRGB8888, GBM_BO_USE_SCANOUT | GBM_BO_USE_CURSOR | GBM_BO_USE_WRITE | GBM_BO_USE_LINEAR},
- {GBM_FORMAT_ARGB8888, GBM_BO_USE_SCANOUT | GBM_BO_USE_CURSOR | GBM_BO_USE_WRITE | GBM_BO_USE_LINEAR},
- /* Blocklinear support */
- {GBM_FORMAT_XRGB8888, GBM_BO_USE_SCANOUT | GBM_BO_USE_RENDERING},
- {GBM_FORMAT_ARGB8888, GBM_BO_USE_SCANOUT | GBM_BO_USE_RENDERING},
+ int ret;
+ struct drm_tegra_gem_mmap gem_map;
+
+ memset(&gem_map, 0, sizeof(gem_map));
+ gem_map.handle = bo->handles[0].u32;
+
+ ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map,
+ sizeof(gem_map));
+ if (ret < 0) {
+ fprintf(stderr, "drv: DRM_TEGRA_GEM_MMAP failed\n");
+ return MAP_FAILED;
}
+
+ data->length = bo->total_size;
+
+ return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
+ bo->drv->fd, gem_map.offset);
+}
+
+struct backend backend_tegra =
+{
+ .name = "tegra",
+ .init = tegra_init,
+ .bo_create = tegra_bo_create,
+ .bo_destroy = drv_gem_bo_destroy,
+ .bo_map = tegra_bo_map,
};
#endif
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