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minigbm: cros_gralloc: back out of scanout flag with more clarity
[android-x86/external-minigbm.git] / tegra.c
diff --git a/tegra.c b/tegra.c
index 91348b1..f48352e 100644 (file)
--- a/tegra.c
+++ b/tegra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,6 +33,27 @@ enum nv_mem_kind
        NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
 };
 
+enum tegra_map_type {
+       TEGRA_READ_TILED_BUFFER = 0,
+       TEGRA_WRITE_TILED_BUFFER = 1,
+};
+
+struct tegra_private_map_data {
+       void *tiled;
+       void *untiled;
+};
+
+static struct supported_combination combos[4] = {
+       {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+       {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+       {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
+       {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+               BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
+};
+
 static int compute_block_height_log2(int height)
 {
        int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
@@ -56,7 +77,7 @@ static void compute_layout_blocklinear(int width, int height, int format,
                                       uint32_t *block_height_log2,
                                       uint32_t *stride, uint32_t *size)
 {
-       int pitch = drv_stride_from_format(format, width);
+       int pitch = drv_stride_from_format(format, width, 0);
 
        /* Align to blocklinear blocks. */
        pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
@@ -83,19 +104,95 @@ static void compute_layout_blocklinear(int width, int height, int format,
 static void compute_layout_linear(int width, int height, int format,
                                  uint32_t *stride, uint32_t *size)
 {
-       *stride = drv_stride_from_format(format, width);
+       *stride = ALIGN(drv_stride_from_format(format, width, 0), 64);
        *size = *stride * height;
 }
 
-static int drv_tegra_bo_create(struct bo *bo, uint32_t width,
-                              uint32_t height, uint32_t format, uint32_t flags)
+static void transfer_tile(struct bo *bo, uint8_t *tiled, uint8_t *untiled,
+                         enum tegra_map_type type, uint32_t bytes_per_pixel,
+                         uint32_t gob_top, uint32_t gob_left,
+                         uint32_t gob_size_pixels)
+{
+       uint8_t *tmp;
+       uint32_t x, y, k;
+       for (k = 0; k < gob_size_pixels; k++) {
+               /*
+                * Given the kth pixel starting from the tile specified by
+                * gob_top and gob_left, unswizzle to get the standard (x, y)
+                * representation.
+                */
+               x = gob_left + (((k >> 3) & 8) | ((k >> 1) & 4) | (k & 3));
+               y = gob_top + ((k >> 7 << 3) | ((k >> 3) & 6) | ((k >> 2) & 1));
+
+               tmp = untiled + (y * bo->strides[0]) + (x * bytes_per_pixel);
+
+               if (type == TEGRA_READ_TILED_BUFFER)
+                       memcpy(tmp, tiled, bytes_per_pixel);
+               else if (type == TEGRA_WRITE_TILED_BUFFER)
+                       memcpy(tiled, tmp, bytes_per_pixel);
+
+               /* Move on to next pixel. */
+               tiled += bytes_per_pixel;
+       }
+}
+
+static void transfer_tiled_memory(struct bo *bo, uint8_t *tiled,
+                                 uint8_t *untiled, enum tegra_map_type type)
+{
+       uint32_t gob_width, gob_height, gob_size_bytes, gob_size_pixels,
+                gob_count_x, gob_count_y, gob_top, gob_left;
+       uint32_t i, j, offset;
+       uint8_t *tmp;
+       uint32_t bytes_per_pixel = drv_stride_from_format(bo->format, 1, 0);
+
+       /*
+        * The blocklinear format consists of 8*(2^n) x 64 byte sized tiles,
+        * where 0 <= n <= 4.
+        */
+       gob_width = DIV_ROUND_UP(NV_BLOCKLINEAR_GOB_WIDTH, bytes_per_pixel);
+       gob_height = NV_BLOCKLINEAR_GOB_HEIGHT *
+                    (1 << NV_DEFAULT_BLOCK_HEIGHT_LOG2);
+       /* Calculate the height from maximum possible gob height */
+       while (gob_height > NV_BLOCKLINEAR_GOB_HEIGHT
+              && gob_height >= 2 * bo->height)
+               gob_height /= 2;
+
+       gob_size_bytes = gob_height * NV_BLOCKLINEAR_GOB_WIDTH;
+       gob_size_pixels = gob_height * gob_width;
+
+       gob_count_x = DIV_ROUND_UP(bo->strides[0], NV_BLOCKLINEAR_GOB_WIDTH);
+       gob_count_y = DIV_ROUND_UP(bo->height, gob_height);
+
+       offset = 0;
+       for (j = 0; j < gob_count_y; j++) {
+               gob_top = j * gob_height;
+               for (i = 0; i < gob_count_x; i++) {
+                       tmp = tiled + offset;
+                       gob_left = i * gob_width;
+
+                       transfer_tile(bo, tmp, untiled, type, bytes_per_pixel,
+                                     gob_top, gob_left, gob_size_pixels);
+
+                       offset += gob_size_bytes;
+               }
+       }
+}
+
+static int tegra_init(struct driver *drv)
+{
+       drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
+       return drv_add_kms_flags(drv);
+}
+
+static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height,
+                          uint32_t format, uint32_t flags)
 {
        uint32_t size, stride, block_height_log2 = 0;
        enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
        struct drm_tegra_gem_create gem_create;
        int ret;
 
-       if (flags & DRV_BO_USE_RENDERING)
+       if (flags & BO_USE_RENDERING)
                compute_layout_blocklinear(width, height, format, &kind,
                                           &block_height_log2, &stride, &size);
        else
@@ -114,7 +211,7 @@ static int drv_tegra_bo_create(struct bo *bo, uint32_t width,
 
        bo->handles[0].u32 = gem_create.handle;
        bo->offsets[0] = 0;
-       bo->sizes[0] = size;
+       bo->total_size = bo->sizes[0] = size;
        bo->strides[0] = stride;
 
        if (kind != NV_MEM_KIND_PITCH) {
@@ -135,16 +232,17 @@ static int drv_tegra_bo_create(struct bo *bo, uint32_t width,
                /* Encode blocklinear parameters for EGLImage creation. */
                bo->tiling = (kind & 0xff) |
                             ((block_height_log2 & 0xf) << 8);
-               bo->format_modifiers[0] = drv_fourcc_mod_code(NV, bo->tiling);
+               bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
        }
 
        return 0;
 }
 
-static void *drv_tegra_bo_map(struct bo *bo)
+static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane)
 {
        int ret;
        struct drm_tegra_gem_mmap gem_map;
+       struct tegra_private_map_data *priv;
 
        memset(&gem_map, 0, sizeof(gem_map));
        gem_map.handle = bo->handles[0].u32;
@@ -156,24 +254,48 @@ static void *drv_tegra_bo_map(struct bo *bo)
                return MAP_FAILED;
        }
 
-       return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED,
-                   bo->drv->fd, gem_map.offset);
+       void *addr = mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
+                         bo->drv->fd, gem_map.offset);
+
+       data->length = bo->total_size;
+
+       if ((bo->tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) {
+               priv = calloc(1, sizeof(*priv));
+               priv->untiled = calloc(1, bo->total_size);
+               priv->tiled = addr;
+               data->priv = priv;
+               transfer_tiled_memory(bo, priv->tiled, priv->untiled,
+                                     TEGRA_READ_TILED_BUFFER);
+               addr = priv->untiled;
+       }
+
+       return addr;
 }
 
-const struct backend backend_tegra =
+static int tegra_bo_unmap(struct bo *bo, struct map_info *data)
+{
+       if (data->priv) {
+               struct tegra_private_map_data *priv = data->priv;
+               transfer_tiled_memory(bo, priv->tiled, priv->untiled,
+                                     TEGRA_WRITE_TILED_BUFFER);
+               data->addr = priv->tiled;
+               free(priv->untiled);
+               free(priv);
+               data->priv = NULL;
+       }
+
+       return munmap(data->addr, data->length);
+}
+
+struct backend backend_tegra =
 {
        .name = "tegra",
-       .bo_create = drv_tegra_bo_create,
+       .init = tegra_init,
+       .bo_create = tegra_bo_create,
        .bo_destroy = drv_gem_bo_destroy,
-       .bo_map = drv_tegra_bo_map,
-       .format_list = {
-               /* Linear support */
-               {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR},
-               {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR},
-               /* Blocklinear support */
-               {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
-               {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
-       }
+       .bo_import = drv_prime_bo_import,
+       .bo_map = tegra_bo_map,
+       .bo_unmap = tegra_bo_unmap,
 };
 
 #endif