Update to LLVM 3.5a.

[android-x86/external-llvm.git] / test / CodeGen / ARM / vqshrn.ll

diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll
index 5da7943..f02482c 100644 (file)
--- a/test/CodeGen/ARM/vqshrn.ll
+++ b/test/CodeGen/ARM/vqshrn.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
 
 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrns8:
+;CHECK-LABEL: vqshrns8:
 ;CHECK: vqshrn.s16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrns16:
+;CHECK-LABEL: vqshrns16:
 ;CHECK: vqshrn.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrns32:
+;CHECK-LABEL: vqshrns32:
 ;CHECK: vqshrn.s64
        %tmp1 = load <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -25,7 +25,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrnu8:
+;CHECK-LABEL: vqshrnu8:
 ;CHECK: vqshrn.u16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -33,7 +33,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrnu16:
+;CHECK-LABEL: vqshrnu16:
 ;CHECK: vqshrn.u32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -41,7 +41,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrnu32:
+;CHECK-LABEL: vqshrnu32:
 ;CHECK: vqshrn.u64
        %tmp1 = load <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -49,7 +49,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshruns8:
+;CHECK-LABEL: vqshruns8:
 ;CHECK: vqshrun.s16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -57,7 +57,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshruns16:
+;CHECK-LABEL: vqshruns16:
 ;CHECK: vqshrun.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -65,7 +65,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshruns32:
+;CHECK-LABEL: vqshruns32:
 ;CHECK: vqshrun.s64
        %tmp1 = load <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -85,7 +85,7 @@ declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind
 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrns8:
+;CHECK-LABEL: vqrshrns8:
 ;CHECK: vqrshrn.s16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -93,7 +93,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrns16:
+;CHECK-LABEL: vqrshrns16:
 ;CHECK: vqrshrn.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -101,7 +101,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrns32:
+;CHECK-LABEL: vqrshrns32:
 ;CHECK: vqrshrn.s64
        %tmp1 = load <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -109,7 +109,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrnu8:
+;CHECK-LABEL: vqrshrnu8:
 ;CHECK: vqrshrn.u16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -117,7 +117,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrnu16:
+;CHECK-LABEL: vqrshrnu16:
 ;CHECK: vqrshrn.u32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -125,7 +125,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrnu32:
+;CHECK-LABEL: vqrshrnu32:
 ;CHECK: vqrshrn.u64
        %tmp1 = load <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -133,7 +133,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshruns8:
+;CHECK-LABEL: vqrshruns8:
 ;CHECK: vqrshrun.s16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -141,7 +141,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshruns16:
+;CHECK-LABEL: vqrshruns16:
 ;CHECK: vqrshrun.s32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -149,7 +149,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshruns32:
+;CHECK-LABEL: vqrshruns32:
 ;CHECK: vqrshrun.s64
        %tmp1 = load <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)