Update aosp/master LLVM for rebase to r256229

[android-x86/external-llvm.git] / test / CodeGen / PowerPC / vsx-fma-m.ll

diff --git a/test/CodeGen/PowerPC/vsx-fma-m.ll b/test/CodeGen/PowerPC/vsx-fma-m.ll
index 9dff9a7..4f556b6 100644 (file)
--- a/test/CodeGen/PowerPC/vsx-fma-m.ll
+++ b/test/CodeGen/PowerPC/vsx-fma-m.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
+; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
 
 ; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the
 ; live-interval-updating logic.
@@ -11,7 +12,7 @@ entry:
   %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 1
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx1, align 8
   ret void
 
@@ -22,6 +23,15 @@ entry:
 ; CHECK-DAG: stxsdx 3, 0, 7
 ; CHECK-DAG: stxsdx 1, 7, [[C1]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @test1
+; CHECK-FISL-DAG: fmr 0, 1
+; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
+; CHECK-FISL-DAG: stxsdx 0, 0, 7
+; CHECK-FISL-DAG: xsmaddadp 1, 2, 4
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
+; CHECK-FISL-DAG: stxsdx 1, 7, [[C1]]
+; CHECK-FISL: blr
 }
 
 define void @test2(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
@@ -29,23 +39,37 @@ entry:
   %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 1
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx1, align 8
   %2 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
-  %arrayidx2 = getelementptr inbounds double* %d, i64 2
+  %arrayidx2 = getelementptr inbounds double, double* %d, i64 2
   store double %2, double* %arrayidx2, align 8
   ret void
 
 ; CHECK-LABEL: @test2
 ; CHECK-DAG: li [[C1:[0-9]+]], 8
 ; CHECK-DAG: li [[C2:[0-9]+]], 16
-; CHECK-DAG: xsmaddmdp 3, 2, 1
-; CHECK-DAG: xsmaddmdp 4, 2, 1
-; CHECK-DAG: xsmaddadp 1, 2, 5
-; CHECK-DAG: stxsdx 3, 0, 8
-; CHECK-DAG: stxsdx 4, 8, [[C1]]
-; CHECK-DAG: stxsdx 1, 8, [[C2]]
+; FIXME: We no longer get this because of copy ordering at the MI level.
+; CHECX-DAG: xsmaddmdp 3, 2, 1
+; CHECX-DAG: xsmaddmdp 4, 2, 1
+; CHECX-DAG: xsmaddadp 1, 2, 5
+; CHECX-DAG: stxsdx 3, 0, 8
+; CHECX-DAG: stxsdx 4, 8, [[C1]]
+; CHECX-DAG: stxsdx 1, 8, [[C2]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @test2
+; CHECK-FISL-DAG: fmr 0, 1
+; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
+; CHECK-FISL-DAG: stxsdx 0, 0, 8
+; CHECK-FISL-DAG: fmr 0, 1
+; CHECK-FISL-DAG: xsmaddadp 0, 2, 4
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
+; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]
+; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
+; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
+; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
+; CHECK-FISL: blr
 }
 
 define void @test3(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
@@ -54,12 +78,12 @@ entry:
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
   %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 3
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 3
   store double %2, double* %arrayidx1, align 8
   %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
-  %arrayidx2 = getelementptr inbounds double* %d, i64 2
+  %arrayidx2 = getelementptr inbounds double, double* %d, i64 2
   store double %3, double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %d, i64 1
+  %arrayidx3 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx3, align 8
   ret void
 
@@ -75,12 +99,26 @@ entry:
 ; re-ordering the instructions.
 ; CHECK-DAG: xsmaddadp [[F1]], 2, 3
 
-; CHECK-DAG: xsmaddmdp 2, 3, 4
+; CHECK-DAG: xsmaddmdp 3, 2, 4
 ; CHECK-DAG: stxsdx [[F1]], 0, 8
-; CHECK-DAG: stxsdx 2, 8, [[C1]]
+; CHECK-DAG: stxsdx 3, 8, [[C1]]
 ; CHECK-DAG: stxsdx 1, 8, [[C2]]
 ; CHECK-DAG: stxsdx 4, 8, [[C3]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @test3
+; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
+; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4
+; CHECK-FISL-DAG: fmr 4, [[F1]]
+; CHECK-FISL-DAG: xsmaddadp 4, 2, 3
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24
+; CHECK-FISL-DAG: stxsdx 4, 8, [[C1]]
+; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
+; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
+; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
+; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8
+; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]
+; CHECK-FISL: blr
 }
 
 define void @test4(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
@@ -88,13 +126,13 @@ entry:
   %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 1
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx1, align 8
   %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
-  %arrayidx3 = getelementptr inbounds double* %d, i64 3
+  %arrayidx3 = getelementptr inbounds double, double* %d, i64 3
   store double %2, double* %arrayidx3, align 8
   %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
-  %arrayidx4 = getelementptr inbounds double* %d, i64 2
+  %arrayidx4 = getelementptr inbounds double, double* %d, i64 2
   store double %3, double* %arrayidx4, align 8
   ret void
 
@@ -116,6 +154,22 @@ entry:
 ; CHECK-DAG: stxsdx 4, 8, [[C3]]
 ; CHECK-DAG: stxsdx 1, 8, [[C2]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @test4
+; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
+; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 3
+; CHECK-FISL-DAG: stxsdx 0, 0, 8
+; CHECK-FISL-DAG: fmr [[F1]], 1
+; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4
+; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8
+; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]
+; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24
+; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]
+; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
+; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
+; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
+; CHECK-FISL: blr
 }
 
 declare double @llvm.fma.f64(double, double, double) #0
@@ -125,7 +179,7 @@ entry:
   %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx1, align 8
   ret void
 
@@ -136,6 +190,15 @@ entry:
 ; CHECK-DAG: stxvd2x 36, 0, 3
 ; CHECK-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @testv1
+; CHECK-FISL-DAG: xxlor 0, 34, 34
+; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
+; CHECK-FISL-DAG: stxvd2x 0, 0, 3
+; CHECK-FISL-DAG: xvmaddadp 34, 35, 37
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
+; CHECK-FISL-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
+; CHECK-FISL: blr
 }
 
 define void @testv2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
@@ -143,23 +206,37 @@ entry:
   %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx1, align 8
   %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
-  %arrayidx2 = getelementptr inbounds <2 x double>* %d, i64 2
+  %arrayidx2 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
   store <2 x double> %2, <2 x double>* %arrayidx2, align 8
   ret void
 
 ; CHECK-LABEL: @testv2
-; CHECK-DAG: xvmaddmdp 36, 35, 34
-; CHECK-DAG: xvmaddmdp 37, 35, 34
-; CHECK-DAG: li [[C1:[0-9]+]], 16
-; CHECK-DAG: li [[C2:[0-9]+]], 32
-; CHECK-DAG: xvmaddadp 34, 35, 38
-; CHECK-DAG: stxvd2x 36, 0, 3
-; CHECK-DAG: stxvd2x 37, 3, [[C1:[0-9]+]]
-; CHECK-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
+; FIXME: We currently don't get this because of copy ordering on the MI level.
+; CHECX-DAG: xvmaddmdp 36, 35, 34
+; CHECX-DAG: xvmaddmdp 37, 35, 34
+; CHECX-DAG: li [[C1:[0-9]+]], 16
+; CHECX-DAG: li [[C2:[0-9]+]], 32
+; CHECX-DAG: xvmaddadp 34, 35, 38
+; CHECX-DAG: stxvd2x 36, 0, 3
+; CHECX-DAG: stxvd2x 37, 3, [[C1:[0-9]+]]
+; CHECX-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @testv2
+; CHECK-FISL-DAG: xxlor 0, 34, 34
+; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
+; CHECK-FISL-DAG: stxvd2x 0, 0, 3
+; CHECK-FISL-DAG: xxlor 0, 34, 34
+; CHECK-FISL-DAG: xvmaddadp 0, 35, 37
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
+; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1:[0-9]+]]
+; CHECK-FISL-DAG: xvmaddadp 34, 35, 38
+; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
+; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
+; CHECK-FISL: blr
 }
 
 define void @testv3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
@@ -168,12 +245,12 @@ entry:
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
   %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 3
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 3
   store <2 x double> %2, <2 x double>* %arrayidx1, align 8
   %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
-  %arrayidx2 = getelementptr inbounds <2 x double>* %d, i64 2
+  %arrayidx2 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
   store <2 x double> %3, <2 x double>* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx3 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx3, align 8
   ret void
 
@@ -201,6 +278,23 @@ entry:
 ; CHECK-DAG: stxvd2x 34, 3, [[C2]]
 ; CHECK-DAG: stxvd2x 37, 3, [[C3]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @testv3
+; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34
+; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36
+; CHECK-FISL-DAG: stxvd2x [[V1]], 0, 3
+; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34
+; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37
+; CHECK-FISL-DAG: xxlor [[V3:[0-9]+]], 0, 0
+; CHECK-FISL-DAG: xvmaddadp [[V3]], 35, 36
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 48
+; CHECK-FISL-DAG: stxvd2x [[V3]], 3, [[C1]]
+; CHECK-FISL-DAG: xvmaddadp 34, 35, 38
+; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
+; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]
+; CHECK-FISL-DAG: li [[C3:[0-9]+]], 16
+; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]
+; CHECK-FISL: blr
 }
 
 define void @testv4(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
@@ -208,13 +302,13 @@ entry:
   %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx1, align 8
   %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
-  %arrayidx3 = getelementptr inbounds <2 x double>* %d, i64 3
+  %arrayidx3 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 3
   store <2 x double> %2, <2 x double>* %arrayidx3, align 8
   %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
-  %arrayidx4 = getelementptr inbounds <2 x double>* %d, i64 2
+  %arrayidx4 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
   store <2 x double> %3, <2 x double>* %arrayidx4, align 8
   ret void
 
@@ -236,6 +330,22 @@ entry:
 ; CHECK-DAG: stxvd2x 37, 3, [[C3]]
 ; CHECK-DAG: stxvd2x 34, 3, [[C2]]
 ; CHECK: blr
+
+; CHECK-FISL-LABEL: @testv4
+; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34
+; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36
+; CHECK-FISL-DAG: stxvd2x 0, 0, 3
+; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34
+; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37
+; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
+; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1]]
+; CHECK-FISL-DAG: xvmaddadp 0, 35, 37
+; CHECK-FISL-DAG: li [[C3:[0-9]+]], 48
+; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]
+; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
+; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
+; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]
+; CHECK-FISL: blr
 }
 
 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0