projects clean up 1

[pinoc/pinoc.git] / test / elf_analyze_test / test2 / test2 / intprg.c

diff --git a/test/elf_analyze_test/test2/test2/intprg.c b/test/elf_analyze_test/test2/test2/intprg.c
new file mode 100644 (file)
index 0000000..089b243
--- /dev/null
+++ b/test/elf_analyze_test/test2/test2/intprg.c
@@ -0,0 +1,144 @@
+/***********************************************************************/
+/*                                                                     */
+/*  FILE        :intprg.c                                              */
+/*  DATE        :Thu, Feb 28, 2013                                     */
+/*  DESCRIPTION :Interrupt Program                                     */
+/*  CPU TYPE    :H8/3069R                                              */
+/*                                                                     */
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */
+/*                                                                     */
+/***********************************************************************/
+                  
+
+
+
+#include    <machine.h>
+#pragma section IntPRG
+//  vector 1 Reserved
+
+//  vector 2 Reserved
+
+//  vector 3 Reserved
+
+//  vector 4 Reserved
+
+//  vector 5 Reserved 
+
+//  vector 6 Reserved
+
+//  vector 7 NMI 
+__interrupt(vect=7) void INT_NMI(void) {/* sleep(); */}
+//  vector 8 TRAP
+__interrupt(vect=8) void INT_TRAP1(void) {/* sleep(); */}
+//  vector 9 TRAP
+__interrupt(vect=9) void INT_TRAP2(void) {/* sleep(); */}
+//  vector 10 TRAP
+__interrupt(vect=10) void INT_TRAP3(void) {/* sleep(); */}
+//  vector 11 TRAP
+__interrupt(vect=11) void INT_TRAP4(void) {/* sleep(); */}
+//  vector 12 IRQ0
+__interrupt(vect=12) void INT_IRQ0(void) {/* sleep(); */}
+//  vector 13 IRQ1
+__interrupt(vect=13) void INT_IRQ1(void) {/* sleep(); */}
+//  vector 14 IRQ2
+__interrupt(vect=14) void INT_IRQ2(void) {/* sleep(); */}
+//  vector 15 IRQ3
+__interrupt(vect=15) void INT_IRQ3(void) {/* sleep(); */}
+//  vector 16 IRQ4
+__interrupt(vect=16) void INT_IRQ4(void) {/* sleep(); */}
+//  vector 17 IRQ5
+__interrupt(vect=17) void INT_IRQ5(void) {/* sleep(); */}
+//  vector 18 Reserved
+
+//  vector 19 Reserved
+
+//  vector 20 WOVI
+__interrupt(vect=20) void INT_WOVI(void) {/* sleep(); */}
+//  vector 21 CMI
+__interrupt(vect=21) void INT_CMI(void) {/* sleep(); */}
+//  vector 22 Reserved
+
+//  vector 23 ADI
+__interrupt(vect=23) void INT_ADI(void) {/* sleep(); */}
+//  vector 24 IMIA0
+__interrupt(vect=24) void INT_IMIA0(void) {/* sleep(); */}
+//  vector 25 IMIB0
+__interrupt(vect=25) void INT_IMIB0(void) {/* sleep(); */}
+//  vector 26 OVI0
+__interrupt(vect=26) void INT_OVI0(void) {/* sleep(); */}
+//  vector 27 Reserved
+
+//  vector 28 IMIA1
+__interrupt(vect=28) void INT_IMIA1(void) {/* sleep(); */}
+//  vector 29 IMIB1
+__interrupt(vect=29) void INT_IMIB1(void) {/* sleep(); */}
+//  vector 30 OVI1
+__interrupt(vect=30) void INT_OVI1(void) {/* sleep(); */}
+//  vector 31 Reserved
+
+//  vector 32 IMIA2
+__interrupt(vect=32) void INT_IMIA2(void) {/* sleep(); */}
+//  vector 33 IMIB2
+__interrupt(vect=33) void INT_IMIB2(void) {/* sleep(); */}
+//  vector 34 OVI2
+__interrupt(vect=34) void INT_OVI2(void) {/* sleep(); */}
+//  vector 35 Reserved
+
+//  vector 36 CMIA0
+__interrupt(vect=36) void INT_CMIA0(void) {/* sleep(); */}
+//  vector 37 CMIB0
+__interrupt(vect=37) void INT_CMIB0(void) {/* sleep(); */}
+//  vector 38 CMIA1B1
+__interrupt(vect=38) void INT_CMIA1B1(void) {/* sleep(); */}
+//  vector 39 TOVI0_1
+__interrupt(vect=39) void INT_TOVI0_1(void) {/* sleep(); */}
+//  vector 40 CMIA2
+__interrupt(vect=40) void INT_CMIA2(void) {/* sleep(); */}
+//  vector 41 CMIB2
+__interrupt(vect=41) void INT_CMIB2(void) {/* sleep(); */}
+//  vector 42 CMIA3B3
+__interrupt(vect=42) void INT_CMIA3B3(void) {/* sleep(); */}
+//  vector 43 TOVI2_3
+__interrupt(vect=43) void INT_TOVI2_3(void) {/* sleep(); */}
+//  vector 44 DEND0A
+__interrupt(vect=44) void INT_DEND0A(void) {/* sleep(); */}
+//  vector 45 DEND0B
+__interrupt(vect=45) void INT_DEND0B(void) {/* sleep(); */}
+//  vector 46 DEND1A
+__interrupt(vect=46) void INT_DEND1A(void) {/* sleep(); */}
+//  vector 47 DEND1B
+__interrupt(vect=47) void INT_DEND1B(void) {/* sleep(); */}
+//  vector 48 Reserved
+
+//  vector 49 Reserved
+
+//  vector 50 Reserved
+
+//  vector 51 Reserved
+
+//  vector 52 ERI0
+__interrupt(vect=52) void INT_ERI0(void) {/* sleep(); */}
+//  vector 53 RXI0
+__interrupt(vect=53) void INT_RXI0(void) {/* sleep(); */}
+//  vector 54 TXI0
+__interrupt(vect=54) void INT_TXI0(void) {/* sleep(); */}
+//  vector 55 TEI0
+__interrupt(vect=55) void INT_TEI0(void) {/* sleep(); */}
+//  vector 56 ERI1
+__interrupt(vect=56) void INT_ERI1(void) {/* sleep(); */}
+//  vector 57 RXI1
+__interrupt(vect=57) void INT_RXI1(void) {/* sleep(); */}
+//  vector 58 TXI1
+__interrupt(vect=58) void INT_TXI1(void) {/* sleep(); */}
+//  vector 59 TEI1
+__interrupt(vect=59) void INT_TEI1(void) {/* sleep(); */}
+//  vector 60 ERI2
+__interrupt(vect=60) void INT_ERI2(void) {/* sleep(); */}
+//  vector 61 RXI2
+__interrupt(vect=61) void INT_RXI2(void) {/* sleep(); */}
+//  vector 62 TXI2
+__interrupt(vect=62) void INT_TXI2(void) {/* sleep(); */}
+//  vector 63 TEI2
+__interrupt(vect=63) void INT_TEI2(void) {/* sleep(); */}
+
+