test/amdgpu: add GDS, GWS and OA tests

[android-x86/external-libdrm.git] / tests / amdgpu / amdgpu_test.h

diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 6287573..0609a74 100644 (file)
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -30,7 +30,7 @@
 /**
  * Define max. number of card in system which we are able to handle
  */
-#define MAX_CARDS_SUPPORTED     4
+#define MAX_CARDS_SUPPORTED     128
 
 /* Forward reference for array to keep "drm" handles */
 extern int drm_amdgpu[MAX_CARDS_SUPPORTED];
@@ -207,11 +207,9 @@ static inline amdgpu_bo_handle gpu_mem_alloc(
                                        amdgpu_va_handle *va_handle)
 {
        struct amdgpu_bo_alloc_request req = {0};
-       amdgpu_bo_handle buf_handle;
+       amdgpu_bo_handle buf_handle = NULL;
        int r;
 
-       CU_ASSERT_NOT_EQUAL(vmc_addr, NULL);
-
        req.alloc_size = size;
        req.phys_alignment = alignment;
        req.preferred_heap = type;
@@ -219,17 +217,36 @@ static inline amdgpu_bo_handle gpu_mem_alloc(
 
        r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
        CU_ASSERT_EQUAL(r, 0);
+       if (r)
+               return NULL;
+
+       if (vmc_addr && va_handle) {
+               r = amdgpu_va_range_alloc(device_handle,
+                                         amdgpu_gpu_va_range_general,
+                                         size, alignment, 0, vmc_addr,
+                                         va_handle, 0);
+               CU_ASSERT_EQUAL(r, 0);
+               if (r)
+                       goto error_free_bo;
+
+               r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0,
+                                   AMDGPU_VA_OP_MAP);
+               CU_ASSERT_EQUAL(r, 0);
+               if (r)
+                       goto error_free_va;
+       }
 
-       r = amdgpu_va_range_alloc(device_handle,
-                                 amdgpu_gpu_va_range_general,
-                                 size, alignment, 0, vmc_addr,
-                                 va_handle, 0);
+       return buf_handle;
+
+error_free_va:
+       r = amdgpu_va_range_free(*va_handle);
        CU_ASSERT_EQUAL(r, 0);
 
-       r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
+error_free_bo:
+       r = amdgpu_bo_free(buf_handle);
        CU_ASSERT_EQUAL(r, 0);
 
-       return buf_handle;
+       return NULL;
 }
 
 static inline int gpu_mem_free(amdgpu_bo_handle bo,
@@ -239,16 +256,26 @@ static inline int gpu_mem_free(amdgpu_bo_handle bo,
 {
        int r;
 
-       r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
-       CU_ASSERT_EQUAL(r, 0);
+       if (!bo)
+               return 0;
 
-       r = amdgpu_va_range_free(va_handle);
-       CU_ASSERT_EQUAL(r, 0);
+       if (va_handle) {
+               r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0,
+                                   AMDGPU_VA_OP_UNMAP);
+               CU_ASSERT_EQUAL(r, 0);
+               if (r)
+                       return r;
+
+               r = amdgpu_va_range_free(va_handle);
+               CU_ASSERT_EQUAL(r, 0);
+               if (r)
+                       return r;
+       }
 
        r = amdgpu_bo_free(bo);
        CU_ASSERT_EQUAL(r, 0);
 
-       return 0;
+       return r;
 }
 
 static inline int