#include <fcntl.h>
#include <stdio.h>
#include "xf86drm.h"
-#include <limits.h>
-
-#define PATH_SIZE PATH_MAX
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
static int amdgpu_ras_lookup_id(drmDevicePtr device)
{
- char path[PATH_SIZE];
+ char path[1024];
char str[128];
drmPciBusInfo info;
int i;
for (i = 0; i < MAX_CARDS_SUPPORTED; i++) {
memset(str, 0, sizeof(str));
memset(&info, 0, sizeof(info));
- snprintf(path, PATH_SIZE, "/sys/kernel/debug/dri/%d/name", i);
+ sprintf(path, "/sys/kernel/debug/dri/%d/name", i);
if (get_file_contents(path, str, sizeof(str)) <= 0)
continue;
return -1;
}
+CU_BOOL suite_ras_tests_enable(void)
+{
+ amdgpu_device_handle device_handle;
+ uint32_t major_version;
+ uint32_t minor_version;
+ int i;
+ drmDevicePtr device;
+
+ for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
+ if (amdgpu_device_initialize(drm_amdgpu[i], &major_version,
+ &minor_version, &device_handle))
+ continue;
+
+ if (drmGetDevice2(drm_amdgpu[i],
+ DRM_DEVICE_GET_PCI_REVISION,
+ &device))
+ continue;
+
+ if (device->bustype == DRM_BUS_PCI &&
+ amdgpu_ras_lookup_capability(device_handle)) {
+ amdgpu_device_deinitialize(device_handle);
+ return CU_TRUE;
+ }
+
+ if (amdgpu_device_deinitialize(device_handle))
+ continue;
+ }
+
+ return CU_FALSE;
+}
+
+int suite_ras_tests_init(void)
+{
+ drmDevicePtr device;
+ amdgpu_device_handle device_handle;
+ uint32_t major_version;
+ uint32_t minor_version;
+ uint32_t capability;
+ struct ras_test_mask test_mask;
+ int id;
+ int i;
+ int r;
+
+ for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
+ r = amdgpu_device_initialize(drm_amdgpu[i], &major_version,
+ &minor_version, &device_handle);
+ if (r)
+ continue;
+
+ if (drmGetDevice2(drm_amdgpu[i],
+ DRM_DEVICE_GET_PCI_REVISION,
+ &device)) {
+ amdgpu_device_deinitialize(device_handle);
+ continue;
+ }
+
+ if (device->bustype != DRM_BUS_PCI) {
+ amdgpu_device_deinitialize(device_handle);
+ continue;
+ }
+
+ capability = amdgpu_ras_lookup_capability(device_handle);
+ if (capability == 0) {
+ amdgpu_device_deinitialize(device_handle);
+ continue;
+
+ }
+
+ id = amdgpu_ras_lookup_id(device);
+ if (id == -1) {
+ amdgpu_device_deinitialize(device_handle);
+ continue;
+ }
+
+ test_mask = amdgpu_ras_get_test_mask(device);
+
+ devices[devices_count++] = (struct amdgpu_ras_data) {
+ device_handle, id, capability, test_mask,
+ };
+ }
+
+ if (devices_count == 0)
+ return CUE_SINIT_FAILED;
+
+ return CUE_SUCCESS;
+}
+
+int suite_ras_tests_clean(void)
+{
+ int r;
+ int i;
+ int ret = CUE_SUCCESS;
+
+ for (i = 0; i < devices_count; i++) {
+ r = amdgpu_device_deinitialize(devices[i].device_handle);
+ if (r)
+ ret = CUE_SCLEAN_FAILED;
+ }
+ return ret;
+}
+
+static void amdgpu_ras_disable_test(void);
+static void amdgpu_ras_enable_test(void);
+static void amdgpu_ras_inject_test(void);
+static void amdgpu_ras_query_test(void);
+static void amdgpu_ras_basic_test(void);
+
+CU_TestInfo ras_tests[] = {
+ { "ras basic test", amdgpu_ras_basic_test },
+ { "ras query test", amdgpu_ras_query_test },
+ { "ras inject test", amdgpu_ras_inject_test },
+ { "ras disable test", amdgpu_ras_disable_test },
+#if 0
+ { "ras enable test", amdgpu_ras_enable_test },
+#endif
+ CU_TEST_INFO_NULL,
+};
+
//helpers
static int test_card;
-static char sysfs_path[PATH_SIZE];
-static char debugfs_path[PATH_SIZE];
+static char sysfs_path[1024];
+static char debugfs_path[1024];
static uint32_t ras_mask;
static amdgpu_device_handle device_handle;
-static void set_test_card(int card)
+static int set_test_card(int card)
{
+ int i;
+
test_card = card;
- snprintf(sysfs_path, PATH_SIZE, "/sys/class/drm/card%d/device/ras/", devices[card].id);
- snprintf(debugfs_path, PATH_SIZE, "/sys/kernel/debug/dri/%d/ras/", devices[card].id);
+ sprintf(sysfs_path, "/sys/class/drm/card%d/device/ras/", devices[card].id);
+ sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/ras/", devices[card].id);
ras_mask = devices[card].capability;
device_handle = devices[card].device_handle;
ras_block_mask_inject = devices[card].test_mask.inject_mask;
ras_block_mask_query = devices[card].test_mask.query_mask;
ras_block_mask_basic = devices[card].test_mask.basic_mask;
+
+ return 0;
}
static const char *get_ras_sysfs_root(void)
static int amdgpu_ras_invoke(struct ras_debug_if *data)
{
- char path[PATH_SIZE];
+ char path[1024];
int ret;
- snprintf(path, sizeof(path), "%s", get_ras_debugfs_root());
- strncat(path, "ras_ctrl", sizeof(path) - strlen(path));
+ sprintf(path, "%s%s", get_ras_debugfs_root(), "ras_ctrl");
ret = set_file_contents(path, (char *)data, sizeof(*data))
- sizeof(*data);
unsigned long *ue, unsigned long *ce)
{
char buf[64];
- char name[PATH_SIZE];
+ char name[1024];
+ int ret;
*ue = *ce = 0;
if (amdgpu_ras_is_feature_supported(block) <= 0)
return -1;
- snprintf(name, sizeof(name), "%s", get_ras_sysfs_root());
- strncat(name, ras_block_str(block), sizeof(name) - strlen(name));
- strncat(name, "_err_count", sizeof(name) - strlen(name));
+ sprintf(name, "%s%s%s", get_ras_sysfs_root(), ras_block_str(block), "_err_count");
if (is_file_ok(name, O_RDONLY))
return 0;
inject->head.block = block;
inject->head.type = type;
inject->head.sub_block_index = sub_block;
- strncpy(inject->head.name, ras_block_str(block), sizeof(inject->head.name)-1);
+ strncpy(inject->head.name, ras_block_str(block), 32);
inject->address = address;
inject->value = value;
static void amdgpu_ras_basic_test(void)
{
+ unsigned long ue, ce;
+ char name[1024];
int ret;
int i;
int j;
uint32_t features;
- char path[PATH_SIZE];
+ char path[1024];
ret = is_file_ok("/sys/module/amdgpu/parameters/ras_mask", O_RDONLY);
CU_ASSERT_EQUAL(ret, 0);
sizeof(features), &features);
CU_ASSERT_EQUAL(ret, 0);
- snprintf(path, sizeof(path), "%s", get_ras_debugfs_root());
- strncat(path, "ras_ctrl", sizeof(path) - strlen(path));
-
+ sprintf(path, "%s%s", get_ras_debugfs_root(), "ras_ctrl");
ret = is_file_ok(path, O_WRONLY);
CU_ASSERT_EQUAL(ret, 0);
- snprintf(path, sizeof(path), "%s", get_ras_sysfs_root());
- strncat(path, "features", sizeof(path) - strlen(path));
-
+ sprintf(path, "%s%s", get_ras_sysfs_root(), "features");
ret = is_file_ok(path, O_RDONLY);
CU_ASSERT_EQUAL(ret, 0);
if (!((1 << j) & ras_block_mask_basic))
continue;
- snprintf(path, sizeof(path), "%s", get_ras_sysfs_root());
- strncat(path, ras_block_str(j), sizeof(path) - strlen(path));
- strncat(path, "_err_count", sizeof(path) - strlen(path));
-
+ sprintf(path, "%s%s%s", get_ras_sysfs_root(), ras_block_str(j), "_err_count");
ret = is_file_ok(path, O_RDONLY);
CU_ASSERT_EQUAL(ret, 0);
- snprintf(path, sizeof(path), "%s", get_ras_debugfs_root());
- strncat(path, ras_block_str(j), sizeof(path) - strlen(path));
- strncat(path, "_err_inject", sizeof(path) - strlen(path));
-
+ sprintf(path, "%s%s%s", get_ras_debugfs_root(), ras_block_str(j), "_err_inject");
ret = is_file_ok(path, O_WRONLY);
CU_ASSERT_EQUAL(ret, 0);
}
}
}
-
-CU_TestInfo ras_tests[] = {
- { "ras basic test", amdgpu_ras_basic_test },
- { "ras query test", amdgpu_ras_query_test },
- { "ras inject test", amdgpu_ras_inject_test },
- { "ras disable test", amdgpu_ras_disable_test },
- { "ras enable test", amdgpu_ras_enable_test },
- CU_TEST_INFO_NULL,
-};
-
-CU_BOOL suite_ras_tests_enable(void)
-{
- amdgpu_device_handle device_handle;
- uint32_t major_version;
- uint32_t minor_version;
- int i;
- drmDevicePtr device;
-
- for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
- if (amdgpu_device_initialize(drm_amdgpu[i], &major_version,
- &minor_version, &device_handle))
- continue;
-
- if (drmGetDevice2(drm_amdgpu[i],
- DRM_DEVICE_GET_PCI_REVISION,
- &device))
- continue;
-
- if (device->bustype == DRM_BUS_PCI &&
- amdgpu_ras_lookup_capability(device_handle)) {
- amdgpu_device_deinitialize(device_handle);
- return CU_TRUE;
- }
-
- if (amdgpu_device_deinitialize(device_handle))
- continue;
- }
-
- return CU_FALSE;
-}
-
-int suite_ras_tests_init(void)
-{
- drmDevicePtr device;
- amdgpu_device_handle device_handle;
- uint32_t major_version;
- uint32_t minor_version;
- uint32_t capability;
- struct ras_test_mask test_mask;
- int id;
- int i;
- int r;
-
- for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
- r = amdgpu_device_initialize(drm_amdgpu[i], &major_version,
- &minor_version, &device_handle);
- if (r)
- continue;
-
- if (drmGetDevice2(drm_amdgpu[i],
- DRM_DEVICE_GET_PCI_REVISION,
- &device)) {
- amdgpu_device_deinitialize(device_handle);
- continue;
- }
-
- if (device->bustype != DRM_BUS_PCI) {
- amdgpu_device_deinitialize(device_handle);
- continue;
- }
-
- capability = amdgpu_ras_lookup_capability(device_handle);
- if (capability == 0) {
- amdgpu_device_deinitialize(device_handle);
- continue;
-
- }
-
- id = amdgpu_ras_lookup_id(device);
- if (id == -1) {
- amdgpu_device_deinitialize(device_handle);
- continue;
- }
-
- test_mask = amdgpu_ras_get_test_mask(device);
-
- devices[devices_count++] = (struct amdgpu_ras_data) {
- device_handle, id, capability, test_mask,
- };
- }
-
- if (devices_count == 0)
- return CUE_SINIT_FAILED;
-
- return CUE_SUCCESS;
-}
-
-int suite_ras_tests_clean(void)
-{
- int r;
- int i;
- int ret = CUE_SUCCESS;
-
- for (i = 0; i < devices_count; i++) {
- r = amdgpu_device_deinitialize(devices[i].device_handle);
- if (r)
- ret = CUE_SCLEAN_FAILED;
- }
- return ret;
-}
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