status reg test ok

[motonesfpga/motonesfpga.git] / tools / qt_proj_test5 / cpu_registers.vhd

diff --git a/tools/qt_proj_test5/cpu_registers.vhd b/tools/qt_proj_test5/cpu_registers.vhd
index 27e2aaa..0649103 100644 (file)
--- a/tools/qt_proj_test5/cpu_registers.vhd
+++ b/tools/qt_proj_test5/cpu_registers.vhd
@@ -137,6 +137,8 @@ entity dual_dff is
             dsize : integer := 8
             );
     port (  
+            dbg_out_port    : out std_logic_vector (dsize - 1 downto 0);
+
             clk             : in std_logic;
             res_n           : in std_logic;
             set_n           : in std_logic;
@@ -198,6 +200,8 @@ begin
 
     back_tsb : tri_state_buffer generic map (dsize) 
                     port map(gate_cmd(1), q, back_out_port);
+
+    dbg_out_port <= q;
 end rtl;
 
 
@@ -332,6 +336,13 @@ entity processor_status is
             dsize : integer := 8
             );
     port (  
+    signal dbg_dec_oe_n    : out std_logic;
+    signal dbg_dec_val     : out std_logic_vector (7 downto 0);
+    signal dbg_int_dbus    : out std_logic_vector (7 downto 0);
+    signal dbg_status_val    : out std_logic_vector (7 downto 0);
+    signal dbg_stat_we_n    : out std_logic;
+
+    
             clk         : in std_logic;
             res_n       : in std_logic;
             dec_oe_n    : in std_logic;
@@ -397,6 +408,12 @@ begin
     --carry status for adc/sbc.
     stat_c <= status_val(0);
 
+    dbg_dec_oe_n    <= dec_oe_n    ;
+    --dbg_dec_val     <= dec_val     ;
+    --dbg_int_dbus    <= int_dbus    ;
+    --dbg_status_val <= status_val;
+    dbg_stat_we_n <= we_n;
+
     main_p : process (clk, res_n, we_n, dec_val, int_dbus, 
                             alu_n, alu_v, alu_z, alu_c)
     variable tmp : std_logic_vector (dsize - 1 downto 0);