address latch integration ok

[motonesfpga/motonesfpga.git] / tools / qt_proj_test5 / qt_proj_test5.vhd

diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd
index ab63662..3dd2cec 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/qt_proj_test5.vhd
@@ -134,6 +134,7 @@ architecture rtl of qt_proj_test5 is
             dsize : integer := 8\r
         );\r
         port (  c         : in std_logic;\r
+                we_n      : in std_logic;\r
                 oc_n      : in std_logic;\r
                 d         : in std_logic_vector(dsize - 1 downto 0);\r
                 q         : out std_logic_vector(dsize - 1 downto 0)\r
@@ -172,6 +173,9 @@ architecture rtl of qt_proj_test5 is
     signal pt_ce_n  : std_logic;\r
     signal nt0_ce_n : std_logic;\r
     signal nt1_ce_n : std_logic;\r
+\r
+    signal ale_n       : std_logic;\r
+    signal vga_clk_n   : std_logic;\r
         \r
     signal dbg_ppu_addr_dummy               : std_logic_vector (13 downto 0);\r
     signal dbg_nes_x                        : std_logic_vector (8 downto 0);\r
@@ -192,13 +196,15 @@ begin
     dbg_cpu_clk <= vga_clk;\r
     dbg_ppu_addr <= "00000" & dbg_nes_x;\r
     dbg_d_io <= "000" & dbg_plt_addr;\r
-    dbg_ppu_data <= dbg_plt_data;\r
+    --dbg_ppu_data <= dbg_plt_data;\r
+    dbg_ppu_data <= "00" & vram_a;\r
     dbg_addr <= "00" & v_addr;\r
     dbg_ppu_status <= vram_ad;\r
     dbg_ppu_scrl_x(0) <= ale;\r
     dbg_ppu_scrl_x(1) <= rd_n;\r
     dbg_ppu_scrl_x(2) <= wr_n;\r
     dbg_ppu_scrl_x(3) <= nt0_ce_n;\r
+    dbg_ppu_scrl_x(4) <= vga_clk_n;\r
     \r
     ppu_inst: ppu port map (  \r
         dbg_ppu_ce_n                                        ,\r
@@ -248,8 +254,10 @@ begin
     v_addr (13 downto 8) <= vram_a;\r
 \r
     --transparent d-latch\r
+        ale_n <= not ale;\r
+        vga_clk_n <= not vga_clk;\r
     vram_latch : ls373 generic map (data_size)\r
-                port map(ale, '0', vram_ad, v_addr(7 downto 0));\r
+                port map(vga_clk, ale_n, ale, vram_ad, v_addr(7 downto 0));\r
 \r
     vchr_rom : chr_rom generic map (chr_rom_8k, data_size)\r
             port map (mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);\r
@@ -275,6 +283,7 @@ begin
     ppu_ce_n <= '0';\r
     cpu_addr <= conv_std_logic_vector(ad, 16)(2 downto 0);\r
     cpu_d <= conv_std_logic_vector(dt, 8);\r
+    ale <= 'Z';\r
 end;\r
 procedure ppu_clr is\r
 begin\r
@@ -282,6 +291,7 @@ begin
     cpu_d <= (others => 'Z');\r
     r_nw <= '1';\r
     ppu_ce_n <= '1';\r
+    ale <= '0';\r
 end;\r
 \r
     begin\r
@@ -426,6 +436,7 @@ end;
                     enable_ppu_step_cnt := enable_ppu_step_cnt + 1;\r
 \r
                 else\r
+                    ale <= 'Z';\r
                     init_done := '1';\r
                 end if;\r
             end if;\r