\r
\r
base_clk : in std_logic;\r
+ base_clk_27mhz : in std_logic;\r
rst_n : in std_logic;\r
h_sync_n : out std_logic;\r
v_sync_n : out std_logic;\r
);\r
end component;\r
\r
+ component vga_clk_gen\r
+ PORT\r
+ (\r
+ inclk0 : IN STD_LOGIC := '0';\r
+ c0 : OUT STD_LOGIC \r
+ );\r
+ END component;\r
+\r
signal pos_x : std_logic_vector (8 downto 0);\r
signal pos_y : std_logic_vector (8 downto 0);\r
signal nes_r : std_logic_vector (3 downto 0);\r
signal cpu_clk : std_logic;\r
signal ppu_clk : std_logic;\r
signal vga_clk : std_logic;\r
+ signal vga_clk_pll : std_logic;\r
+ \r
\r
signal addr : std_logic_vector( addr_size - 1 downto 0);\r
signal d_io : std_logic_vector( data_size - 1 downto 0);\r
\r
\r
begin\r
+ --ppu/cpu clock generator\r
+ clock_inst : clock_divider port map \r
+ (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);\r
\r
ppu_inst: dummy_ppu \r
port map ( ppu_clk ,\r
nes_g ,\r
nes_b \r
);\r
+\r
+ vga_clk_gen_inst : vga_clk_gen\r
+ PORT map\r
+ (\r
+ base_clk_27mhz, vga_clk_pll\r
+ );\r
+\r
+ \r
vga_ctl_inst : vga_ctl\r
port map ( ppu_clk ,\r
+ --vga_clk_pll, \r
+ --ppu_clk ,\r
vga_clk ,\r
rst_n ,\r
pos_x ,\r
);\r
\r
\r
- trig_clk <= not cpu_clk;\r
-\r
- pcl_inst : counter_register generic map (16) port map\r
- (cpu_clk, rst_n, '0', '1', (others => '0'), addr(15 downto 0));\r
-\r
- rom_inst : prg_rom generic map (12, 8) port map\r
- (base_clk, '0', addr(11 downto 0), d_io);\r
-\r
- dbg_addr <= addr;\r
- dbg_d_io <= d_io;\r
-\r
- --ppu/cpu clock generator\r
- clock_inst : clock_divider port map \r
- (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);\r
-\r
- dbg_cpu_clk <= cpu_clk;\r
- dbg_ppu_clk <= ppu_clk;\r
-\r
- dbg_d1 <= d1;\r
- dbg_d2 <= d2;\r
- dbg_d_out <= d_out;\r
- dbg_ea_carry <= ea_carry;\r
- dbg_carry_clr_n <= carry_clr_n;\r
- dbg_gate_n <= gate_n;\r
- \r
- dummy_alu : alu_test\r
- port map ( \r
- d1, d2, d_out, carry_clr_n , ea_carry\r
- );\r
-\r
- gate_n <= not ea_carry;\r
- dec_test_p : process (rst_n, ea_carry, trig_clk)\r
- begin\r
- if (rst_n = '0') then\r
- d1 <= "00000000";\r
- d2 <= "00000000";\r
- carry_clr_n <= '0';\r
- --gate_n <= '1';\r
--- elsif (ea_carry = '1') then\r
--- gate_n <= '0';\r
+-- trig_clk <= not cpu_clk;\r
+--\r
+-- pcl_inst : counter_register generic map (16) port map\r
+-- (cpu_clk, rst_n, '0', '1', (others => '0'), addr(15 downto 0));\r
+--\r
+-- rom_inst : prg_rom generic map (12, 8) port map\r
+-- (base_clk, '0', addr(11 downto 0), d_io);\r
+--\r
+-- dbg_addr <= addr;\r
+-- dbg_d_io <= d_io;\r
+--\r
+-- dbg_cpu_clk <= cpu_clk;\r
+-- dbg_ppu_clk <= ppu_clk;\r
+--\r
+-- dbg_d1 <= d1;\r
+-- dbg_d2 <= d2;\r
+-- dbg_d_out <= d_out;\r
+-- dbg_ea_carry <= ea_carry;\r
+-- dbg_carry_clr_n <= carry_clr_n;\r
+-- dbg_gate_n <= gate_n;\r
+-- \r
+-- dummy_alu : alu_test\r
+-- port map ( \r
+-- d1, d2, d_out, carry_clr_n , ea_carry\r
+-- );\r
+--\r
+-- gate_n <= not ea_carry;\r
+-- dec_test_p : process (rst_n, ea_carry, trig_clk)\r
+-- begin\r
+-- if (rst_n = '0') then\r
+-- d1 <= "00000000";\r
+-- d2 <= "00000000";\r
-- carry_clr_n <= '0';\r
- elsif (rising_edge(trig_clk)) then\r
- if (addr(5 downto 0) = "000001") then\r
- --addr=01\r
- carry_clr_n <= '1';\r
- d1 <= "00010011";\r
- d2 <= "01000111";\r
- --gate_n <= '1';\r
- elsif (addr(5 downto 0) = "000010") then\r
- --addr=02\r
- carry_clr_n <= '1';\r
- d1 <= "00110011";\r
- d2 <= "11001111";\r
- --gate_n <= '1';\r
- elsif (addr(5 downto 0) = "000011") then\r
- --addr=03\r
- carry_clr_n <= '1';\r
- d1 <= "00001010";\r
- d2 <= "01011001";\r
- --gate_n <= '1';\r
- elsif (addr(5 downto 0) = "000100") then\r
- --addr=04\r
- carry_clr_n <= '1';\r
- d1 <= "10001010";\r
- d2 <= "10011001";\r
- --gate_n <= '1';\r
- else\r
- carry_clr_n <= '1';\r
- d1 <= "00000000";\r
- d2 <= "00000000";\r
- --gate_n <= '1';\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
- --status register\r
- status_register : processor_status generic map (8) \r
- port map (\r
- dbg_dec_oe_n,\r
- dbg_dec_val,\r
- dbg_int_dbus,\r
- dbg_status_val,\r
- dbg_stat_we_n ,\r
- trig_clk , rst_n, \r
- stat_dec_oe_n, stat_bus_oe_n, \r
- stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n, \r
- stat_alu_we_n, alu_n, alu_v, alu_z, alu_c, stat_c,\r
- status_reg, int_d_bus);\r
-\r
- dbg_status <= status_reg;\r
- status_test_p : process (addr)\r
- begin\r
- if (addr(5 downto 0) = "000010") then\r
- --addr=02\r
- --set status(7) = '1'\r
- stat_dec_oe_n <= '1';\r
- stat_bus_oe_n <= '1';\r
- stat_set_flg_n <= '0';\r
- stat_flg <= '1';\r
- stat_bus_all_n <= '1';\r
- stat_bus_nz_n <= '1'; \r
- stat_alu_we_n <= '1';\r
- status_reg <= "01000000";\r
- int_d_bus <= "00000000";\r
-\r
- elsif (addr(5 downto 0) = "000100") then\r
- --addr=04\r
- --set status(2) = '0'\r
- stat_dec_oe_n <= '1';\r
- stat_bus_oe_n <= '1';\r
- stat_set_flg_n <= '0';\r
- stat_flg <= '0';\r
- stat_bus_all_n <= '1';\r
- stat_bus_nz_n <= '1'; \r
- stat_alu_we_n <= '1';\r
- status_reg <= "00000100";\r
- int_d_bus <= "00000000";\r
-\r
- elsif (addr(5 downto 0) = "000110") then\r
- --addr=06\r
- --set nz from bus, n=1\r
- stat_dec_oe_n <= '1';\r
- stat_bus_oe_n <= '1';\r
- stat_set_flg_n <= '1';\r
- stat_flg <= '0';\r
- stat_bus_all_n <= '1';\r
- stat_bus_nz_n <= '0'; \r
- stat_alu_we_n <= '1';\r
- status_reg <= (others => 'Z');\r
- int_d_bus <= "10000000";\r
-\r
- elsif (addr(5 downto 0) = "001000") then\r
- --addr=08\r
- --set nz from bus, z=1\r
- stat_dec_oe_n <= '1';\r
- stat_bus_oe_n <= '1';\r
- stat_set_flg_n <= '1';\r
- stat_flg <= '0';\r
- stat_bus_all_n <= '1';\r
- stat_bus_nz_n <= '0'; \r
- stat_alu_we_n <= '1';\r
- status_reg <= (others => 'Z');\r
- int_d_bus <= "00000000";\r
-\r
- else\r
- stat_dec_oe_n <= '0';\r
- stat_bus_oe_n <= '1';\r
- stat_set_flg_n <= '1';\r
- stat_flg <= '1';\r
- stat_bus_all_n <= '1';\r
- stat_bus_nz_n <= '1'; \r
- stat_alu_we_n <= '1';\r
- status_reg <= (others => 'Z');\r
- int_d_bus <= (others => 'Z');\r
- end if;\r
- end process;\r
+-- --gate_n <= '1';\r
+---- elsif (ea_carry = '1') then\r
+---- gate_n <= '0';\r
+---- carry_clr_n <= '0';\r
+-- elsif (rising_edge(trig_clk)) then\r
+-- if (addr(5 downto 0) = "000001") then\r
+-- --addr=01\r
+-- carry_clr_n <= '1';\r
+-- d1 <= "00010011";\r
+-- d2 <= "01000111";\r
+-- --gate_n <= '1';\r
+-- elsif (addr(5 downto 0) = "000010") then\r
+-- --addr=02\r
+-- carry_clr_n <= '1';\r
+-- d1 <= "00110011";\r
+-- d2 <= "11001111";\r
+-- --gate_n <= '1';\r
+-- elsif (addr(5 downto 0) = "000011") then\r
+-- --addr=03\r
+-- carry_clr_n <= '1';\r
+-- d1 <= "00001010";\r
+-- d2 <= "01011001";\r
+-- --gate_n <= '1';\r
+-- elsif (addr(5 downto 0) = "000100") then\r
+-- --addr=04\r
+-- carry_clr_n <= '1';\r
+-- d1 <= "10001010";\r
+-- d2 <= "10011001";\r
+-- --gate_n <= '1';\r
+-- else\r
+-- carry_clr_n <= '1';\r
+-- d1 <= "00000000";\r
+-- d2 <= "00000000";\r
+-- --gate_n <= '1';\r
+-- end if;\r
+-- end if;\r
+-- end process;\r
+--\r
+--\r
+-- --status register\r
+-- status_register : processor_status generic map (8) \r
+-- port map (\r
+-- dbg_dec_oe_n,\r
+-- dbg_dec_val,\r
+-- dbg_int_dbus,\r
+-- dbg_status_val,\r
+-- dbg_stat_we_n ,\r
+-- trig_clk , rst_n, \r
+-- stat_dec_oe_n, stat_bus_oe_n, \r
+-- stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n, \r
+-- stat_alu_we_n, alu_n, alu_v, alu_z, alu_c, stat_c,\r
+-- status_reg, int_d_bus);\r
+--\r
+-- dbg_status <= status_reg;\r
+-- status_test_p : process (addr)\r
+-- begin\r
+-- if (addr(5 downto 0) = "000010") then\r
+-- --addr=02\r
+-- --set status(7) = '1'\r
+-- stat_dec_oe_n <= '1';\r
+-- stat_bus_oe_n <= '1';\r
+-- stat_set_flg_n <= '0';\r
+-- stat_flg <= '1';\r
+-- stat_bus_all_n <= '1';\r
+-- stat_bus_nz_n <= '1'; \r
+-- stat_alu_we_n <= '1';\r
+-- status_reg <= "01000000";\r
+-- int_d_bus <= "00000000";\r
+--\r
+-- elsif (addr(5 downto 0) = "000100") then\r
+-- --addr=04\r
+-- --set status(2) = '0'\r
+-- stat_dec_oe_n <= '1';\r
+-- stat_bus_oe_n <= '1';\r
+-- stat_set_flg_n <= '0';\r
+-- stat_flg <= '0';\r
+-- stat_bus_all_n <= '1';\r
+-- stat_bus_nz_n <= '1'; \r
+-- stat_alu_we_n <= '1';\r
+-- status_reg <= "00000100";\r
+-- int_d_bus <= "00000000";\r
+--\r
+-- elsif (addr(5 downto 0) = "000110") then\r
+-- --addr=06\r
+-- --set nz from bus, n=1\r
+-- stat_dec_oe_n <= '1';\r
+-- stat_bus_oe_n <= '1';\r
+-- stat_set_flg_n <= '1';\r
+-- stat_flg <= '0';\r
+-- stat_bus_all_n <= '1';\r
+-- stat_bus_nz_n <= '0'; \r
+-- stat_alu_we_n <= '1';\r
+-- status_reg <= (others => 'Z');\r
+-- int_d_bus <= "10000000";\r
+--\r
+-- elsif (addr(5 downto 0) = "001000") then\r
+-- --addr=08\r
+-- --set nz from bus, z=1\r
+-- stat_dec_oe_n <= '1';\r
+-- stat_bus_oe_n <= '1';\r
+-- stat_set_flg_n <= '1';\r
+-- stat_flg <= '0';\r
+-- stat_bus_all_n <= '1';\r
+-- stat_bus_nz_n <= '0'; \r
+-- stat_alu_we_n <= '1';\r
+-- status_reg <= (others => 'Z');\r
+-- int_d_bus <= "00000000";\r
+--\r
+-- else\r
+-- stat_dec_oe_n <= '0';\r
+-- stat_bus_oe_n <= '1';\r
+-- stat_set_flg_n <= '1';\r
+-- stat_flg <= '1';\r
+-- stat_bus_all_n <= '1';\r
+-- stat_bus_nz_n <= '1'; \r
+-- stat_alu_we_n <= '1';\r
+-- status_reg <= (others => 'Z');\r
+-- int_d_bus <= (others => 'Z');\r
+-- end if;\r
+-- end process;\r
\r
end rtl;\r
\r
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