vga output working...

[motonesfpga/motonesfpga.git] / tools / qt_proj_test5 / qt_proj_test5.vhd

diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd
index 9264fc1..f6b69ca 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/qt_proj_test5.vhd
@@ -194,16 +194,19 @@ end component;
 \r
 \r
 begin\r
+    --ppu/cpu clock generator\r
+    clock_inst : clock_divider port map \r
+        (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);\r
 \r
---    ppu_inst: dummy_ppu \r
---        port map (  ppu_clk     ,\r
---                rst_n       ,\r
---                pos_x       ,\r
---                pos_y       ,\r
---                nes_r       ,\r
---                nes_g       ,\r
---                nes_b       \r
---        );\r
+    ppu_inst: dummy_ppu \r
+        port map (  ppu_clk     ,\r
+                rst_n       ,\r
+                pos_x       ,\r
+                pos_y       ,\r
+                nes_r       ,\r
+                nes_g       ,\r
+                nes_b       \r
+        );\r
 \r
         vga_clk_gen_inst : vga_clk_gen\r
         PORT map\r
@@ -214,8 +217,9 @@ begin
     \r
     vga_ctl_inst : vga_ctl\r
     port map (  ppu_clk     ,\r
-            vga_clk_pll, \r
-            --vga_clk     ,\r
+            --vga_clk_pll, \r
+            --ppu_clk ,\r
+            vga_clk     ,\r
             rst_n       ,\r
             pos_x       ,\r
             pos_y       ,\r
@@ -241,10 +245,6 @@ begin
 --    dbg_addr <= addr;\r
 --    dbg_d_io <= d_io;\r
 --\r
---    --ppu/cpu clock generator\r
---    clock_inst : clock_divider port map \r
---        (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);\r
---\r
 --    dbg_cpu_clk <= cpu_clk;\r
 --    dbg_ppu_clk <= ppu_clk;\r
 --\r