debug env update, chr rom added

[motonesfpga/motonesfpga.git] / tools / qt_proj_test5 / simulation / modelsim / qt_proj_test5_run_msim_gate_vhdl.do

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
index 5aaedbf..2e208e2 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
@@ -18,14 +18,6 @@ add wave  -label ppu_clk sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_clk
 add wave  sim:/testbench_qt_proj_test5/sim_board/rst_n\r
 \r
 \r
-#add wave  sim:/testbench_qt_proj_test5/sim_board/dbg_cpu_clk\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d_io\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_instruction\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_int_d_bus\r
-\r
-\r
-\r
 add wave -divider vga_out\r
 add wave  sim:/testbench_qt_proj_test5/sim_board/v_sync_n\r
 add wave  sim:/testbench_qt_proj_test5/sim_board/h_sync_n\r
@@ -34,13 +26,25 @@ add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/g
 add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/b\r
 \r
 add wave -divider vga_pos\r
-add wave -radix decimal -unsigned  -label vga_x sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_h\r
+add wave -radix decimal -unsigned  -label vga_x sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
 add wave -radix decimal -unsigned  -label nes_x sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_addr\r
 \r
+add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_nt\r
+add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_attr\r
+add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_h\r
+add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_l\r
 \r
 \r
-#add wave -divider status\r
 \r
+#add wave  sim:/testbench_qt_proj_test5/sim_board/dbg_cpu_clk\r
+#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
+#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d_io\r
+#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_instruction\r
+#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_int_d_bus\r
+\r
+\r
+\r
+#add wave -divider status\r
 #add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d1\r
 #add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d2\r
 #add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d_out\r
@@ -51,7 +55,6 @@ add wave -radix decimal -unsigned  -label nes_x sim:/testbench_qt_proj_test5/sim
 \r
 \r
 #add wave -divider status_debug\r
-\r
 #add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_status\r
 #add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_dec_oe_n\r
 #add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_status_val\r