address latch integration ok

[motonesfpga/motonesfpga.git] / tools / qt_proj_test5 / simulation / modelsim / qt_proj_test5_run_msim_rtl_vhdl.do

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do
index dd8f27c..4570d25 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do
@@ -26,19 +26,19 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneii
 \r
 add wave  sim:/testbench_qt_proj_test5/sim_board/rst_n\r
 #add wave  sim:/testbench_qt_proj_test5/base_clk\r
-add wave  -label emu_ppu_clk sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/emu_ppu_clk\r
+#add wave  -label emu_ppu_clk sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/emu_ppu_clk\r
 \r
 \r
 add wave -divider ppu\r
 add wave  -label ppu_ctrl -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/ppu_ctrl\r
 add wave  -label ppu_mask -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/ppu_mask\r
 \r
-add wave -divider vga_pos\r
-add wave  -label nes_x          -radix decimal -unsigned  sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/nes_x\r
-add wave  -label dbg_disp_nt    -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_nt\r
-add wave  -label dbg_disp_attr  -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/disp_attr\r
-add wave  -label dbg_disp_ptn_h -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_h\r
-add wave  -label dbg_disp_ptn_l -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_l\r
+#add wave -divider vga_pos\r
+#add wave  -label nes_x          -radix decimal -unsigned  sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/nes_x\r
+#add wave  -label dbg_disp_nt    -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_nt\r
+#add wave  -label dbg_disp_attr  -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/disp_attr\r
+#add wave  -label dbg_disp_ptn_h -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_h\r
+#add wave  -label dbg_disp_ptn_l -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_l\r
 \r
 add wave -divider vram\r
 \r
@@ -57,6 +57,7 @@ add wave  -label oe_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/oe_n
 add wave  -label we_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/we_n\r
 add wave  -label addr   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_nt0/addr\r
 add wave  -label data   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_nt0/d_io\r
+add wave  -label v_addr   -radix hex sim:/testbench_qt_proj_test5/sim_board/v_addr\r
 \r
 add wave -divider vga_output\r
 add wave  -label h_sync_n   sim:/testbench_qt_proj_test5/sim_board/h_sync_n\r
@@ -68,6 +69,5 @@ add wave  -label b          -radix hex sim:/testbench_qt_proj_test5/sim_board/b
 \r
 view structure\r
 view signals\r
-run 100 us\r
+run 15 us\r
 wave zoom full\r
-\r