debug env update, chr rom added

[motonesfpga/motonesfpga.git] / tools / qt_proj_test5 / vga.vhd

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index c1c41d5..6da3176 100644 (file)
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -15,6 +15,7 @@ entity vga_ctl is
     port (  \r
     signal dbg_ppu_clk                      : out std_logic;\r
     signal dbg_nes_x                        : out std_logic_vector (8 downto 0);\r
+    signal dbg_vga_x                        : out std_logic_vector (9 downto 0);\r
     signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);\r
     signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);\r
 \r
@@ -133,7 +134,6 @@ signal oam_plt_addr    : std_logic_vector (7 downto 0);
 signal oam_plt_data    : std_logic_vector (7 downto 0);\r
 signal v_bus_busy_n    : std_logic;\r
 signal ppu_status      : std_logic_vector (7 downto 0);\r
-signal dbg_disp_ptn_h2, dbg_disp_ptn_l2 : std_logic_vector (15 downto 0);\r
 \r
 ---DE1 base clock 50 MHz\r
 ---motones sim project uses following clock.\r
@@ -143,10 +143,7 @@ signal dbg_disp_ptn_h2, dbg_disp_ptn_l2 : std_logic_vector (15 downto 0);
 --sdram clock = 135 MHz\r
 \r
 begin\r
-\r
-    dbg_disp_ptn_h <= "000000" & vga_x;\r
-    dbg_disp_ptn_l <= "0000000" & nes_x;\r
-\r
+    dbg_vga_x <= vga_x;\r
 \r
     cnt_clk <= not vga_clk;\r
     \r
@@ -254,7 +251,7 @@ begin
         dbg_ppu_clk                      ,\r
         dbg_nes_x                        ,\r
         dbg_disp_nt, dbg_disp_attr      ,\r
-        dbg_disp_ptn_h2, dbg_disp_ptn_l2  ,\r
+        dbg_disp_ptn_h, dbg_disp_ptn_l  ,\r
         \r
                 emu_ppu_clk_n ,\r
                 mem_clk     ,\r