/* Perform SSA transformation for the whole method */
dvmCompilerMethodSSATransformation(&cUnit);
+#ifndef ARCH_IA32
dvmCompilerInitializeRegAlloc(&cUnit); // Needs to happen after SSA naming
/* Allocate Registers using simple local allocation scheme */
dvmCompilerLocalRegAlloc(&cUnit);
+#endif
/* Convert MIR to LIR, etc. */
dvmCompilerMethodMIR2LIR(&cUnit);
*/
dvmCompilerInsertBackwardChaining(cUnit);
+#if defined(ARCH_IA32)
+ /* Convert MIR to LIR, etc. */
+ dvmCompilerMIR2LIR(cUnit, info);
+#else
dvmCompilerInitializeRegAlloc(cUnit);
/* Allocate Registers using simple local allocation scheme */
/* Convert MIR to LIR, etc. */
dvmCompilerMIR2LIR(cUnit);
+#endif
/* Loop contains never executed blocks / heavy instructions */
if (cUnit->quitLoopMode) {
optHints | JIT_OPT_NO_LOOP);
}
+static bool searchClassTablePrefix(const Method* method) {
+ if (gDvmJit.classTable == NULL) {
+ return false;
+ }
+ HashIter iter;
+ HashTable* pTab = gDvmJit.classTable;
+ for (dvmHashIterBegin(pTab, &iter); !dvmHashIterDone(&iter);
+ dvmHashIterNext(&iter))
+ {
+ const char* str = (const char*) dvmHashIterData(&iter);
+ if (strncmp(method->clazz->descriptor, str, strlen(str)) == 0) {
+ return true;
+ }
+ }
+ return false;
+}
+
/*
* Main entry point to start trace compilation. Basic blocks are constructed
* first and they will be passed to the codegen routines to convert Dalvik
dvmInitGrowableList(blockList, 8);
/* Identify traces that we don't want to compile */
+ if (gDvmJit.classTable) {
+ bool classFound = searchClassTablePrefix(desc->method);
+ if (gDvmJit.classTable && gDvmJit.includeSelectedMethod != classFound) {
+ return false;
+ }
+ }
if (gDvmJit.methodTable) {
int len = strlen(desc->method->clazz->descriptor) +
strlen(desc->method->name) + 1;
* 2) If includeSelectedMethod == true, the method does not match the
* full and partial signature stored in the hash table.
*/
- if (gDvmJit.includeSelectedMethod != methodFound) {
+ if (gDvmJit.methodTable && gDvmJit.includeSelectedMethod != methodFound) {
+#ifdef ARCH_IA32
+ return false;
+#else
cUnit.allSingleStep = true;
+#endif
} else {
/* Compile the trace as normal */
}
}
+ // Each pair is a range, check whether curOffset falls into a range.
+ bool includeOffset = (gDvmJit.num_entries_pcTable < 2);
+ for (int pcOff = 0; pcOff < gDvmJit.num_entries_pcTable; ) {
+ if (pcOff+1 >= gDvmJit.num_entries_pcTable) {
+ break;
+ }
+ if (curOffset >= gDvmJit.pcTable[pcOff] && curOffset <= gDvmJit.pcTable[pcOff+1]) {
+ includeOffset = true;
+ break;
+ }
+ pcOff += 2;
+ }
+ if (!includeOffset) {
+ return false;
+ }
+
/* Allocate the entry block */
curBB = dvmCompilerNewBB(kEntryBlock, numBlocks++);
dvmInsertGrowableList(blockList, (intptr_t) curBB);
dvmCompilerNonLoopAnalysis(&cUnit);
+#ifndef ARCH_IA32
dvmCompilerInitializeRegAlloc(&cUnit); // Needs to happen after SSA naming
+#endif
if (cUnit.printMe) {
dvmCompilerDumpCompilationUnit(&cUnit);
}
+#ifndef ARCH_IA32
/* Allocate Registers using simple local allocation scheme */
dvmCompilerLocalRegAlloc(&cUnit);
/* Convert MIR to LIR, etc. */
dvmCompilerMIR2LIR(&cUnit);
+#else /* ARCH_IA32 */
+ /* Convert MIR to LIR, etc. */
+ dvmCompilerMIR2LIR(&cUnit, info);
+#endif
/* Convert LIR into machine code. Loop for recoverable retries */
do {