/* Track exercised opcodes */
static int opcodeCoverage[256];
+static void setMemRefType(ArmLIR *lir, bool isLoad, int memType)
+{
+ u8 *maskPtr;
+ u8 mask;
+ assert( EncodingMap[lir->opCode].flags & (IS_LOAD | IS_STORE));
+ if (isLoad) {
+ maskPtr = &lir->useMask;
+ mask = ENCODE_MEM_USE;
+ } else {
+ maskPtr = &lir->defMask;
+ mask = ENCODE_MEM_DEF;
+ }
+ /* Clear out the memref flags */
+ *maskPtr &= ~mask;
+ /* ..and then add back the one we need */
+ switch(memType) {
+ case kLiteral:
+ assert(isLoad);
+ *maskPtr |= (ENCODE_LITERAL | ENCODE_LITPOOL_REF);
+ break;
+ case kDalvikReg:
+ *maskPtr |= (ENCODE_DALVIK_REG | ENCODE_FRAME_REF);
+ break;
+ case kHeapRef:
+ *maskPtr |= ENCODE_HEAP_REF;
+ break;
+ default:
+ LOGE("Jit: invalid memref kind - %d", memType);
+ assert(0); // Bail if debug build, set worst-case in the field
+ *maskPtr |= ENCODE_ALL;
+ }
+}
+
/*
* Mark load/store instructions that access Dalvik registers through rFP +
* offset.
*/
static void annotateDalvikRegAccess(ArmLIR *lir, int regId, bool isLoad)
{
- if (isLoad) {
- lir->useMask |= ENCODE_DALVIK_REG;
- } else {
- lir->defMask |= ENCODE_DALVIK_REG;
- }
+ setMemRefType(lir, isLoad, kDalvikReg);
/*
* Store the Dalvik register id in aliasInfo. Mark he MSB if it is a 64-bit
flags = EncodingMap[lir->opCode].flags;
/* Set up the mask for resources that are updated */
+ if (flags & (IS_LOAD | IS_STORE)) {
+ /* Default to heap - will catch specialized classes later */
+ setMemRefType(lir, flags & IS_LOAD, kHeapRef);
+ }
+
if (flags & IS_BRANCH) {
lir->defMask |= ENCODE_REG_PC;
lir->useMask |= ENCODE_REG_PC;
lir->defMask |= ENCODE_REG_SP;
}
- if (flags & REG_DEF_SP) {
+ if (flags & REG_DEF_LR) {
lir->defMask |= ENCODE_REG_LR;
}
((mir->next->dalvikInsn.opCode == OP_MOVE_RESULT) ||
(mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_OBJECT))) {
mir->next->dalvikInsn.opCode = OP_NOP;
- return getDestLoc(cUnit, mir->next, 0);
+ return dvmCompilerGetDest(cUnit, mir->next, 0);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL;
res.fp = fpHint;
if (mir->next &&
(mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_WIDE)) {
mir->next->dalvikInsn.opCode = OP_NOP;
- return getDestLocWide(cUnit, mir->next, 0, 1);
+ return dvmCompilerGetDestWide(cUnit, mir->next, 0, 1);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL_WIDE;
res.fp = fpHint;
ArmLIR *pcrLabel)
{
/* Forget all def info (because we might rollback here. Bug #2367397 */
- resetDefTracking(cUnit);
+ dvmCompilerResetDefTracking(cUnit);
/* Set up the place holder to reconstruct this Dalvik PC */
if (pcrLabel == NULL) {
int dPC = (int) (cUnit->method->insns + dOffset);
pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
- pcrLabel->opCode = ARM_PSEUDO_kPCReconstruction_CELL;
+ pcrLabel->opCode = kArmPseudoPCReconstructionCell;
pcrLabel->operands[0] = dPC;
pcrLabel->operands[1] = dOffset;
/* Insert the place holder to the growable list */