FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[AA]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vAA
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* ------------------------------ */
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
b .LOP_SPUT_OBJECT_end
/* ------------------------------ */
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[AA]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vAA
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[AA]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vAA
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[AA]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vAA
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[AA]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vAA
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[AA]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vAA
+ SMP_DMB
GOTO_OPCODE(ip) @ jump to next instruction
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
mov r0, rPC
bl dvmGetOriginalOpcode @ (rPC)
FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
+ ldr r1, [rSELF, #offThread_mainHandlerTable]
and rINST, #0xff00
orr rINST, rINST, r0
- GOTO_OPCODE(r0)
+ GOTO_OPCODE_BASE(r1, r0)
/* ------------------------------ */
.balign 64
ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
b .LOP_SPUT_OBJECT_VOLATILE_end
FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[BBBB]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* ------------------------------ */
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
.endif
ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
b .LOP_SPUT_OBJECT_JUMBO_end
/* ------------------------------ */
FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[BBBB]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[BBBB]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[BBBB]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[BBBB]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
GET_VREG(r1, r2) @ r1<- fp[BBBB]
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ SMP_DMB
GOTO_OPCODE(ip) @ jump to next instruction
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
.endif
ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_WIDE */
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r9, r3 @ r2<- target address
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (32 bits)<- r0
+ @ no-op
cmp r0, #0 @ stored a null reference?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
GOTO_OPCODE(ip) @ jump to next instruction
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_BYTE */
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_CHAR */
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_SHORT */
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_SGET */
.LOP_SPUT_OBJECT_end:
str r1, [r0, #offStaticField_value] @ field<- vAA
+ @ no-op
cmp r1, #0 @ stored a null object?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
GOTO_OPCODE(ip) @ jump to next instruction
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ SMP_DMB
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_SGET_VOLATILE */
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r9, r3 @ r2<- target address
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
str r0, [r9, r3] @ obj.field (32 bits)<- r0
+ SMP_DMB
cmp r0, #0 @ stored a null reference?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
GOTO_OPCODE(ip) @ jump to next instruction
.LOP_SPUT_OBJECT_VOLATILE_end:
str r1, [r0, #offStaticField_value] @ field<- vAA
+ SMP_DMB
cmp r1, #0 @ stored a null object?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
GOTO_OPCODE(ip) @ jump to next instruction
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_WIDE_JUMBO */
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r9, r3 @ r2<- target address
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (32 bits)<- r0
+ @ no-op
cmp r0, #0 @ stored a null reference?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
GOTO_OPCODE(ip) @ jump to next instruction
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_BYTE_JUMBO */
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_CHAR_JUMBO */
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_SHORT_JUMBO */
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- @ no-op @ releasing store
+ @ no-op @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ @ no-op
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_SGET_JUMBO */
.LOP_SPUT_OBJECT_JUMBO_end:
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ @ no-op
cmp r1, #0 @ stored a null object?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
GOTO_OPCODE(ip) @ jump to next instruction
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
+ SMP_DMB
GOTO_OPCODE(ip) @ jump to next instruction
/* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r9, r3 @ r2<- target address
- bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
beq common_errNullObject @ object was null
FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
GET_INST_OPCODE(ip) @ extract opcode from rINST
- SMP_DMB @ releasing store
+ SMP_DMB_ST @ releasing store
str r0, [r9, r3] @ obj.field (32 bits)<- r0
+ SMP_DMB
cmp r0, #0 @ stored a null reference?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
GOTO_OPCODE(ip) @ jump to next instruction
.LOP_SPUT_OBJECT_VOLATILE_JUMBO_end:
str r1, [r0, #offStaticField_value] @ field<- vBBBB
+ SMP_DMB
cmp r1, #0 @ stored a null object?
strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
GOTO_OPCODE(ip) @ jump to next instruction
/* ------------------------------ */
.balign 64
.L_ALT_OP_DISPATCH_FF: /* 0xff */
-/* File: armv5te/alt_stub.S */
+/* File: armv5te/ALT_OP_DISPATCH_FF.S */
/*
- * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
- * any interesting requests and then jump to the real instruction
- * handler. Note that the call to dvmCheckBefore is done as a tail call.
- * rIBASE updates won't be seen until a refresh, and we can tell we have a
- * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
- * bail to the real handler if breakFlags==0.
+ * Unlike other alt stubs, we don't want to call dvmCheckBefore() here.
+ * Instead, just treat this as a trampoline to reach the real alt
+ * handler (which will do the dvmCheckBefore() call.
*/
- ldrb r3, [rSELF, #offThread_breakFlags]
- adrl lr, dvmAsmInstructionStart + (255 * 64)
- ldr rIBASE, [rSELF, #offThread_curHandlerTable]
- cmp r3, #0
- bxeq lr @ nothing to do - jump to real handler
- EXPORT_PC()
- mov r0, rPC @ arg0
- mov r1, rFP @ arg1
- mov r2, rSELF @ arg2
- b dvmCheckBefore @ (dPC,dFP,self) tail call
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
+ add ip, ip, #256 @ add offset for extended opcodes
+ GOTO_OPCODE(ip) @ go to proper extended handler
+
/* ------------------------------ */
.balign 64
mov r1, #1
str r1, [rSELF,#offThread_singleStepCount] @ just step once
mov r0, rSELF
- mov r1, #kInterpSingleStep
- mov r2, #kSubModeNormal
- mov r3, #1 @ true
- bl dvmUpdateInterpBreak @ (self, newBreak, newMode, enable)
+ mov r1, #kSubModeCountedStep
+ bl dvmEnableSubMode @ (self, newMode)
ldr rIBASE, [rSELF,#offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
* r2 is jit state.
*/
common_selectTrace:
- ldrb r0,[rSELF,#offThread_breakFlags]
- ands r0,#kInterpJitBreak
+ ldrh r0,[rSELF,#offThread_subMode]
+ ands r0, #(kSubModeJitTraceBuild | kSubModeJitSV)
bne 3f @ already doing JIT work, continue
str r2,[rSELF,#offThread_jitState]
mov r0, rSELF
beq 1f
@ Set up SV single-stepping
mov r0, rSELF
- mov r1, #kInterpJitBreak
- mov r2, #kSubModeJitSV
- mov r3, #1 @ true
- bl dvmUpdateInterpBreak @ (self, newBreak, newMode, enable)
+ mov r1, #kSubModeJitSV
+ bl dvmEnableSubMode @ (self, subMode)
mov r2,#kJitSelfVerification @ ask for self verification
str r2,[rSELF,#offThread_jitState]
@ intentional fallthrough
cmp lr, #0 @ any special SubModes active?
bne 11f @ go handle them if so
- mov lr, pc @ set return addr
- ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
+ ldr ip, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
+ blx ip
7:
@ native return; r10=newSaveArea
ldmfd sp, {r0-r3} @ refresh. NOTE: no sp autoincrement
@ Call the native method
- mov lr, pc @ set return addr
- ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
+ ldr ip, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
+ blx ip
@ Restore the pre-call arguments
ldmfd sp!, {r0-r3} @ r2<- methodToCall (others unneeded)
.LstrSqueak:
.asciz "<%d>"
.LstrPrintHex:
- .asciz "<0x%x>"
+ .asciz "<%#x>"
.LstrPrintLong:
.asciz "<%lld>"