X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;ds=sidebyside;f=amdgpu.c;h=795d13790602ba6668585fe5c40adb65ce91da8d;hb=aead8fab07ce8eaf2568eefdc11520a36b989d10;hp=ee05009a36ae7ad0ebee252b026e3c9d2d41d80f;hpb=29d742e7d64baa2b50cf262dbad2db752c883238;p=android-x86%2Fexternal-minigbm.git diff --git a/amdgpu.c b/amdgpu.c index ee05009..795d137 100644 --- a/amdgpu.c +++ b/amdgpu.c @@ -13,415 +13,314 @@ #include #include -#include "addrinterface.h" +#include "dri.h" #include "drv_priv.h" #include "helpers.h" #include "util.h" -#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND -#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A -#endif - // clang-format off -#define mmCC_RB_BACKEND_DISABLE 0x263d -#define mmGB_TILE_MODE0 0x2644 -#define mmGB_MACROTILE_MODE0 0x2664 -#define mmGB_ADDR_CONFIG 0x263e -#define mmMC_ARB_RAMCFG 0x9d8 - -enum { - FAMILY_UNKNOWN, - FAMILY_SI, - FAMILY_CI, - FAMILY_KV, - FAMILY_VI, - FAMILY_CZ, - FAMILY_PI, - FAMILY_LAST, -}; +#define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so) // clang-format on -const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_XRGB8888 }; +#define TILE_TYPE_LINEAR 0 +/* DRI backend decides tiling in this case. */ +#define TILE_TYPE_DRI 1 -const static uint32_t texture_source_formats[] = { DRM_FORMAT_NV21, DRM_FORMAT_NV12 }; +struct amdgpu_priv { + struct dri_driver dri; + int drm_version; +}; -static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info) -{ - struct drm_amdgpu_gem_metadata args = { 0 }; +const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888 }; - if (!info) - return -EINVAL; +const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, + DRM_FORMAT_NV21, DRM_FORMAT_NV12, + DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 }; - args.handle = handle; - args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA; - args.data.flags = info->flags; - args.data.tiling_info = info->tiling_info; +static int amdgpu_init(struct driver *drv) +{ + struct amdgpu_priv *priv; + drmVersionPtr drm_version; + struct format_metadata metadata; + uint64_t use_flags = BO_USE_RENDER_MASK; - if (info->size_metadata > sizeof(args.data.data)) - return -EINVAL; + priv = calloc(1, sizeof(struct amdgpu_priv)); + if (!priv) + return -ENOMEM; - if (info->size_metadata) { - args.data.data_size_bytes = info->size_metadata; - memcpy(args.data.data, info->umd_metadata, info->size_metadata); + drm_version = drmGetVersion(drv_get_fd(drv)); + if (!drm_version) { + free(priv); + return -ENODEV; } - return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args)); -} + priv->drm_version = drm_version->version_minor; + drmFreeVersion(drm_version); -static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance, - uint32_t flags, uint32_t *values) -{ - struct drm_amdgpu_info request; - - memset(&request, 0, sizeof(request)); - request.return_pointer = (uintptr_t)values; - request.return_size = count * sizeof(uint32_t); - request.query = AMDGPU_INFO_READ_MMR_REG; - request.read_mmr_reg.dword_offset = dword_offset; - request.read_mmr_reg.count = count; - request.read_mmr_reg.instance = instance; - request.read_mmr_reg.flags = flags; - - return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info)); -} + drv->priv = priv; -static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info) -{ - int ret; - uint32_t instance; + if (dri_init(drv, DRI_PATH, "radeonsi")) { + free(priv); + drv->priv = NULL; + return -ENODEV; + } - if (!gpu_info) - return -EINVAL; + metadata.tiling = TILE_TYPE_LINEAR; + metadata.priority = 1; + metadata.modifier = DRM_FORMAT_MOD_LINEAR; - instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT; + drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), + &metadata, use_flags); - ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0, - &gpu_info->backend_disable[0]); - if (ret) - return ret; - /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */ - gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff; + drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), + &metadata, BO_USE_TEXTURE_MASK); - ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode); - if (ret) - return ret; + /* + * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the + * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future. + */ + drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER); + drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_HW_VIDEO_ENCODER); - ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0, - gpu_info->gb_macro_tile_mode); - if (ret) - return ret; + /* Android CTS tests require this. */ + drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); - ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg); - if (ret) - return ret; + /* Linear formats supported by display. */ + drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); - ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg); - if (ret) - return ret; + /* YUV formats for camera and display. */ + drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, + BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT | + BO_USE_HW_VIDEO_DECODER); + + drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT); + + /* + * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots + * from camera. + */ + drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, + BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); + + /* + * The following formats will be allocated by the DRI backend and may be potentially tiled. + * Since format modifier support hasn't been implemented fully yet, it's not + * possible to enumerate the different types of buffers (like i915 can). + */ + use_flags &= ~BO_USE_RENDERSCRIPT; + use_flags &= ~BO_USE_SW_WRITE_OFTEN; + use_flags &= ~BO_USE_SW_READ_OFTEN; + use_flags &= ~BO_USE_LINEAR; + + metadata.tiling = TILE_TYPE_DRI; + metadata.priority = 2; + drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), + &metadata, use_flags); + + /* Potentially tiled formats supported by display. */ + drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); return 0; } -static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in) +static void amdgpu_close(struct driver *drv) { - return malloc(in->sizeInBytes); + dri_close(drv); + free(drv->priv); + drv->priv = NULL; } -static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in) +static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, + uint64_t use_flags) { - free(in->pVirtAddr); - return ADDR_OK; -} + int ret; + uint32_t plane, stride; + union drm_amdgpu_gem_create gem_create; -static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format, - uint32_t usage, uint32_t *tiling_flags, - ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out) -{ - ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 }; - ADDR_TILEINFO addr_tile_info = { 0 }; - ADDR_TILEINFO addr_tile_info_out = { 0 }; - uint32_t bits_per_pixel; - - addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT); - - /* Set the requested tiling mode. */ - addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1; - if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN)) - addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED; - else if (width <= 16 || height <= 16) - addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1; - - bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8; - /* Bits per pixel should be calculated from format*/ - addr_surf_info_in.bpp = bits_per_pixel; - addr_surf_info_in.numSamples = 1; - addr_surf_info_in.width = width; - addr_surf_info_in.height = height; - addr_surf_info_in.numSlices = 1; - addr_surf_info_in.pTileInfo = &addr_tile_info; - addr_surf_info_in.tileIndex = -1; - - /* This disables incorrect calculations (hacks) in addrlib. */ - addr_surf_info_in.flags.noStencil = 1; - - /* Set the micro tile type. */ - if (usage & BO_USE_SCANOUT) - addr_surf_info_in.tileType = ADDR_DISPLAYABLE; - else - addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE; + stride = drv_stride_from_format(format, width, 0); + stride = ALIGN(stride, 256); - addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT); - addr_out->pTileInfo = &addr_tile_info_out; + drv_bo_from_format(bo, stride, height, format); - if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK) - return -EINVAL; + memset(&gem_create, 0, sizeof(gem_create)); + gem_create.in.bo_size = bo->meta.total_size; + gem_create.in.alignment = 256; + gem_create.in.domain_flags = 0; - ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 }; - ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 }; - ADDR_TILEINFO s_tile_hw_info_out = { 0 }; + if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK)) + gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT); - /* Convert from real value to HW value */ - s_in.reverse = 0; - s_in.pTileInfo = &addr_tile_info_out; - s_in.tileIndex = -1; + gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; + if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT))) + gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; - s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT); - s_out.pTileInfo = &s_tile_hw_info_out; + /* Allocate the buffer with the preferred heap. */ + ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create, + sizeof(gem_create)); + if (ret < 0) + return ret; - if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK) - return -EINVAL; + for (plane = 0; plane < bo->meta.num_planes; plane++) + bo->handles[plane].u32 = gem_create.out.handle; - if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1) - /* 2D_TILED_THIN1 */ - *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); - else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1) - /* 1D_TILED_THIN1 */ - *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); - else - /* LINEAR_ALIGNED */ - *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); - - *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth)); - *tiling_flags |= - AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight)); - *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes); - *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, - drv_log_base2(addr_tile_info_out.macroAspectRatio)); - *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig); - *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks); + bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR; return 0; } -static void *amdgpu_addrlib_init(int fd) +static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, + uint64_t use_flags) { - int ret; - ADDR_CREATE_INPUT addr_create_input = { 0 }; - ADDR_CREATE_OUTPUT addr_create_output = { 0 }; - ADDR_REGISTER_VALUE reg_value = { 0 }; - ADDR_CREATE_FLAGS create_flags = { { 0 } }; - ADDR_E_RETURNCODE addr_ret; - - addr_create_input.size = sizeof(ADDR_CREATE_INPUT); - addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT); + struct combination *combo; - struct amdgpu_gpu_info gpu_info = { 0 }; + combo = drv_get_combination(bo->drv, format, use_flags); + if (!combo) + return -EINVAL; - ret = amdgpu_query_gpu(fd, &gpu_info); + if (combo->metadata.tiling == TILE_TYPE_DRI) { + bool needs_alignment = false; +#ifdef __ANDROID__ + /* + * Currently, the gralloc API doesn't differentiate between allocation time and map + * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at + * allocation time. + * + * See b/115946221,b/117942643 + */ + if (use_flags & (BO_USE_SW_MASK)) + needs_alignment = true; +#endif + // See b/122049612 + if (use_flags & (BO_USE_SCANOUT)) + needs_alignment = true; - if (ret) { - fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret); - return NULL; - } + if (needs_alignment) { + uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0); + width = ALIGN(width, 256 / bytes_per_pixel); + } - reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3; - reg_value.gbAddrConfig = gpu_info.gb_addr_cfg; - reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2; - - reg_value.backendDisables = gpu_info.backend_disable[0]; - reg_value.pTileConfig = gpu_info.gb_tile_mode; - reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]); - reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode; - reg_value.noOfMacroEntries = - sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]); - create_flags.value = 0; - create_flags.useTileIndex = 1; - - addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND; - - addr_create_input.chipFamily = FAMILY_CZ; - addr_create_input.createFlags = create_flags; - addr_create_input.callbacks.allocSysMem = alloc_sys_mem; - addr_create_input.callbacks.freeSysMem = free_sys_mem; - addr_create_input.callbacks.debugPrint = 0; - addr_create_input.regValue = reg_value; - - addr_ret = AddrCreate(&addr_create_input, &addr_create_output); - - if (addr_ret != ADDR_OK) { - fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret); - return NULL; + return dri_bo_create(bo, width, height, format, use_flags); } - return addr_create_output.hLib; + return amdgpu_create_bo_linear(bo, width, height, format, use_flags); } -static int amdgpu_init(struct driver *drv) +static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height, + uint32_t format, const uint64_t *modifiers, + uint32_t count) { - int ret; - void *addrlib; - struct format_metadata metadata; - uint32_t flags = BO_USE_RENDER_MASK; - - addrlib = amdgpu_addrlib_init(drv_get_fd(drv)); - if (!addrlib) - return -1; - - drv->priv = addrlib; - - ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), - &LINEAR_METADATA, BO_USE_TEXTURE_MASK); - if (ret) - return ret; + bool only_use_linear = true; - drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT); - drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT); + for (uint32_t i = 0; i < count; ++i) + if (modifiers[i] != DRM_FORMAT_MOD_LINEAR) + only_use_linear = false; - metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED; - metadata.priority = 2; - metadata.modifier = DRM_FORMAT_MOD_NONE; - - ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, flags); - if (ret) - return ret; - - drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); - drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); - drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); - - metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED; - metadata.priority = 3; - metadata.modifier = DRM_FORMAT_MOD_NONE; - - ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, flags); - if (ret) - return ret; - - flags &= ~BO_USE_SW_WRITE_OFTEN; - flags &= ~BO_USE_SW_READ_OFTEN; - flags &= ~BO_USE_LINEAR; - - metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1; - metadata.priority = 4; - - ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, flags); - if (ret) - return ret; - - drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT); - drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT); - drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); + if (only_use_linear) + return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT); - metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1; - metadata.priority = 5; - - ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, flags); - if (ret) - return ret; - - return ret; -} - -static void amdgpu_close(struct driver *drv) -{ - AddrDestroy(drv->priv); - drv->priv = NULL; + return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count); } -static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, - uint32_t usage) +static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data) { - void *addrlib = bo->drv->priv; - union drm_amdgpu_gem_create gem_create; - struct amdgpu_bo_metadata metadata = { 0 }; - ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 }; - uint32_t tiling_flags = 0; - uint32_t gem_create_flags = 0; - size_t plane; - int ret; - - if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) { - drv_bo_from_format(bo, ALIGN(width, 64), height, format); - } else { - if (amdgpu_addrlib_compute(addrlib, width, height, format, usage, &tiling_flags, - &addr_out) < 0) + bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR; + if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) { + struct combination *combo; + combo = drv_get_combination(bo->drv, data->format, data->use_flags); + if (!combo) return -EINVAL; - bo->tiling = tiling_flags; - /* RGB has 1 plane only */ - bo->offsets[0] = 0; - bo->total_size = bo->sizes[0] = addr_out.surfSize; - bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8); + dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI; } - if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | - BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY)) - gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + if (dri_tiling) + return dri_bo_import(bo, data); else - gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; - - memset(&gem_create, 0, sizeof(gem_create)); - - gem_create.in.bo_size = bo->total_size; - gem_create.in.alignment = addr_out.baseAlign; - /* Set the placement. */ - gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM; - gem_create.in.domain_flags = gem_create_flags; - /* Allocate the buffer with the preferred heap. */ - ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create, - sizeof(gem_create)); - - if (ret < 0) - return ret; - - metadata.tiling_info = tiling_flags; - - for (plane = 0; plane < bo->num_planes; plane++) - bo->handles[plane].u32 = gem_create.out.handle; - - ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata); + return drv_prime_bo_import(bo, data); +} - return ret; +static int amdgpu_destroy_bo(struct bo *bo) +{ + if (bo->priv) + return dri_bo_destroy(bo); + else + return drv_gem_bo_destroy(bo); } -static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane) +static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) { int ret; union drm_amdgpu_gem_mmap gem_map; + if (bo->priv) + return dri_bo_map(bo, vma, plane, map_flags); + memset(&gem_map, 0, sizeof(gem_map)); gem_map.in.handle = bo->handles[plane].u32; ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); if (ret) { - fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); + drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); return MAP_FAILED; } - data->length = bo->total_size; - return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd, + vma->length = bo->meta.total_size; + + return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, gem_map.out.addr_ptr); } -static uint32_t amdgpu_resolve_format(uint32_t format) +static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma) +{ + if (bo->priv) + return dri_bo_unmap(bo, vma); + else + return munmap(vma->addr, vma->length); +} + +static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping) +{ + int ret; + union drm_amdgpu_gem_wait_idle wait_idle; + + if (bo->priv) + return 0; + + memset(&wait_idle, 0, sizeof(wait_idle)); + wait_idle.in.handle = bo->handles[0].u32; + wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE; + + ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle, + sizeof(wait_idle)); + + if (ret < 0) { + drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret); + return ret; + } + + if (ret == 0 && wait_idle.out.status) + drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n"); + + return 0; +} + +static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags) { switch (format) { + case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: + /* Camera subsystem requires NV12. */ + if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) + return DRM_FORMAT_NV12; + /*HACK: See b/28671744 */ + return DRM_FORMAT_XBGR8888; case DRM_FORMAT_FLEX_YCbCr_420_888: return DRM_FORMAT_NV12; default: @@ -429,15 +328,19 @@ static uint32_t amdgpu_resolve_format(uint32_t format) } } -struct backend backend_amdgpu = { +const struct backend backend_amdgpu = { .name = "amdgpu", .init = amdgpu_init, .close = amdgpu_close, - .bo_create = amdgpu_bo_create, - .bo_destroy = drv_gem_bo_destroy, - .bo_import = drv_prime_bo_import, - .bo_map = amdgpu_bo_map, + .bo_create = amdgpu_create_bo, + .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers, + .bo_destroy = amdgpu_destroy_bo, + .bo_import = amdgpu_import_bo, + .bo_map = amdgpu_map_bo, + .bo_unmap = amdgpu_unmap_bo, + .bo_invalidate = amdgpu_bo_invalidate, .resolve_format = amdgpu_resolve_format, + .num_planes_from_modifier = dri_num_planes_from_modifier, }; #endif