X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=VGADisplay%2FVerilog%2Fvga_gen.v;h=032501ef108bbf23b8ce04c28b706b2d2110b45c;hb=HEAD;hp=b2b6de794ef0f0c3514e6416a08fd305c5c14fa6;hpb=f480c1ee33749f635678adf74f2d3a2efc2fab63;p=oca1%2Ftest.git

diff --git a/VGADisplay/Verilog/vga_gen.v b/VGADisplay/Verilog/vga_gen.v
index b2b6de7..032501e 100644
--- a/VGADisplay/Verilog/vga_gen.v
+++ b/VGADisplay/Verilog/vga_gen.v
@@ -1,6 +1,6 @@
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:48:34 2011
- Licensed to :LIMITED EVALUATION USER:
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:30:56 2012
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:
 */
 
 module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_dummy_rgb , o_vcnt , i_wrdata , fi_fifo_write , o_rdack , o_led );
@@ -112,20 +112,18 @@ module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync ,
   reg _reg_59;
   reg _reg_60;
   reg _reg_61;
-  reg _reg_62;
+  wire _net_62;
   wire _net_63;
   wire _net_64;
   wire _net_65;
-  wire _net_66;
-  wire _net_67;
-  reg _reg_68;
-  reg _reg_69;
-  wire _net_70;
+  reg _reg_66;
+  reg _reg_67;
+  wire _net_68;
 vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));
 
-   assign  fs_fifo_read = _net_63|_reg_60|_net_15;
+   assign  fs_fifo_read = _reg_60|_net_15;
    assign  w_rddata = _u_FIFO_o_rddata;
-   assign  fs_fifo_ack = _reg_68;
+   assign  fs_fifo_ack = _reg_66;
    assign  fs_initialize = _net_0;
    assign  _u_FIFO_i_rst = i_fifo_rst;
    assign  _u_FIFO_i_clk50 = i_clk50;
@@ -191,12 +189,11 @@ vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u
    assign  _net_55 = (r_vcnt)==(10'b0111101011);
    assign  _net_56 = (r_vcnt)==(10'b0111101001);
    assign  _net_57 = (r_vcnt)==(10'b0111100000);
-   assign  _net_63 = fs_initialize|_reg_62;
-   assign  _net_64 = fs_initialize|_reg_61|_reg_62;
-   assign  _net_65 = fs_initialize|_reg_60|_reg_61;
-   assign  _net_66 = fs_initialize|_reg_59|_reg_60;
-   assign  _net_67 = fs_initialize|_reg_58|_reg_59;
-   assign  _net_70 = fs_fifo_read|_reg_68|_reg_69;
+   assign  _net_62 = fs_initialize|_reg_61;
+   assign  _net_63 = fs_initialize|_reg_60|_reg_61;
+   assign  _net_64 = fs_initialize|_reg_59|_reg_60;
+   assign  _net_65 = fs_initialize|_reg_58|_reg_59;
+   assign  _net_68 = fs_fifo_read|_reg_66|_reg_67;
    assign  o_vsync = r_vsync;
    assign  o_hsync = r_hsync;
    assign  o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|
@@ -215,8 +212,8 @@ always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
      r_data1 <= 8'b00000000;
-else if ((_reg_61)|(_net_51|_net_16)) 
-      r_data1 <= ((_reg_61) ?_u_FIFO_o_rddata:8'b0)|
+else if ((_net_62)|(_net_51|_net_16)) 
+      r_data1 <= ((_net_62) ?_u_FIFO_o_rddata:8'b0)|
     ((_net_51|_net_16) ?w_rddata:8'b0);
 
 end
@@ -355,53 +352,46 @@ always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
      _reg_58 <= 1'b0;
-else if ((_net_67)) 
+else if ((_net_65)) 
       _reg_58 <= _reg_59;
 end
 always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
      _reg_59 <= 1'b0;
-else if ((_net_66)) 
+else if ((_net_64)) 
       _reg_59 <= _reg_60;
 end
 always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
      _reg_60 <= 1'b0;
-else if ((_net_65)) 
-      _reg_60 <= _reg_61;
+else if ((_net_63)) 
+      _reg_60 <= _reg_61|fs_initialize;
 end
 always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
      _reg_61 <= 1'b0;
-else if ((_net_64)) 
-      _reg_61 <= _reg_62|fs_initialize;
-end
-always @(posedge m_clock or posedge p_reset)
-  begin
-if (p_reset)
-     _reg_62 <= 1'b0;
-else if ((_reg_62)) 
-      _reg_62 <= 1'b0;
+else if ((_reg_61)) 
+      _reg_61 <= 1'b0;
 end
 always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
-     _reg_68 <= 1'b0;
-else if ((_net_70)) 
-      _reg_68 <= _reg_69|fs_fifo_read;
+     _reg_66 <= 1'b0;
+else if ((_net_68)) 
+      _reg_66 <= _reg_67|fs_fifo_read;
 end
 always @(posedge m_clock or posedge p_reset)
   begin
 if (p_reset)
-     _reg_69 <= 1'b0;
-else if ((_reg_69)) 
-      _reg_69 <= 1'b0;
+     _reg_67 <= 1'b0;
+else if ((_reg_67)) 
+      _reg_67 <= 1'b0;
 end
 endmodule
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:48:39 2011
- Licensed to :LIMITED EVALUATION USER:
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:01 2012
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com 
 */