X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=VGADisplay%2FVerilog%2Fvram_ctrl.v;fp=VGADisplay%2FVerilog%2Fvram_ctrl.v;h=87dd8aa5748e439f90fa6d43c72d6d56d4aa7367;hb=142e6e2c632d28f5fe778002afd7f1090195dec7;hp=b2a6a66a98e2439dc34aa03c4b3df37b814a6e6e;hpb=045f3fe5341583b785a56a3faedccdb5fe5c688d;p=oca1%2Ftest.git

diff --git a/VGADisplay/Verilog/vram_ctrl.v b/VGADisplay/Verilog/vram_ctrl.v
index b2a6a66..87dd8aa 100644
--- a/VGADisplay/Verilog/vram_ctrl.v
+++ b/VGADisplay/Verilog/vram_ctrl.v
@@ -1,5 +1,5 @@
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:23 2011
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Aug 12 17:25:22 2011
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:
 */
 
@@ -13,11 +13,11 @@ module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , f
   input fi_Rd_req;
   output fo_Rd_ack;
   reg [13:0] r_Radrs_hld;
-  wire _u_VRAM_clk;
-  wire [7:0] _u_VRAM_d;
-  wire [13:0] _u_VRAM_ra;
-  wire [13:0] _u_VRAM_wa;
-  wire _u_VRAM_we;
+  wire _u_VRAM_clock;
+  wire [7:0] _u_VRAM_data;
+  wire [13:0] _u_VRAM_rdaddress;
+  wire [13:0] _u_VRAM_wraddress;
+  wire _u_VRAM_wren;
   wire [7:0] _u_VRAM_q;
   wire _u_VRAM_p_reset;
   wire _u_VRAM_m_clock;
@@ -26,40 +26,41 @@ module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , f
   reg _reg_2;
   wire _net_3;
   wire _net_4;
-vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk));
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));
 
-   assign  _u_VRAM_d = i_Wdata;
-   assign  _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)|
+   assign  _u_VRAM_clock = m_clock;
+   assign  _u_VRAM_data = i_Wdata;
+   assign  _u_VRAM_rdaddress = ((_net_3)?i_Radrs:14'b0)|
     ((_reg_1)?r_Radrs_hld:14'b0);
-   assign  _u_VRAM_wa = i_Wadrs;
-   assign  _u_VRAM_we = fi_Wr_req|
+   assign  _u_VRAM_wraddress = i_Wadrs;
+   assign  _u_VRAM_wren = fi_Wr_req|
     ((_net_0)?1'b0:1'b0);
    assign  _net_0 = ~fi_Wr_req;
    assign  _net_3 = fi_Rd_req|_reg_2;
    assign  _net_4 = fi_Rd_req|_reg_1|_reg_2;
    assign  o_Rdata = _u_VRAM_q;
    assign  fo_Rd_ack = _reg_1;
-always @(posedge p_reset)
+always @(negedge p_reset)
  begin
-if (p_reset)
+if (~p_reset)
      r_Radrs_hld <= 14'b00000000000000;
 end
-always @(posedge m_clock or posedge p_reset)
+always @(posedge m_clock or negedge p_reset)
   begin
-if (p_reset)
+if (~p_reset)
      _reg_1 <= 1'b0;
 else if ((_net_4)) 
       _reg_1 <= _reg_2|fi_Rd_req;
 end
-always @(posedge m_clock or posedge p_reset)
+always @(posedge m_clock or negedge p_reset)
   begin
-if (p_reset)
+if (~p_reset)
      _reg_2 <= 1'b0;
 else if ((_reg_2)) 
       _reg_2 <= 1'b0;
 end
 endmodule
 /*
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:25 2011
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Aug 12 17:25:23 2011
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp 
 */