X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=amdgpu%2Famdgpu.h;h=1901fa8c6867ebb1f067e87705bc99162680046b;hb=41be41f99eb53bd4998b1cd930fa63f0e552d971;hp=027b549b4227d2cf6cf4c02ab2f16e7a4f6e7ee6;hpb=f91b56dc8c604ec1c6f092d69550266d20dc9764;p=android-x86%2Fexternal-libdrm.git diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 027b549b..1901fa8c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -19,7 +19,7 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * -*/ + */ /** * \file amdgpu.h @@ -37,6 +37,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + struct drm_amdgpu_info_hw_ip; /*--------------------------------------------------------------------------*/ @@ -57,7 +61,7 @@ struct drm_amdgpu_info_hw_ip; #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull /** - * Used in amdgpu_cs_query_fence::flags, meaning that the given timeout + * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout * is absolute. */ #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) @@ -124,6 +128,11 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; */ typedef struct amdgpu_va *amdgpu_va_handle; +/** + * Define handle for semaphore + */ +typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; + /*--------------------------------------------------------------------------*/ /* -------------------------- Structures ---------------------------------- */ /*--------------------------------------------------------------------------*/ @@ -156,19 +165,6 @@ struct amdgpu_bo_alloc_request { }; /** - * Structure describing memory allocation request - * - * \sa amdgpu_bo_alloc() -*/ -struct amdgpu_bo_alloc_result { - /** Assigned virtual MC Base Address */ - uint64_t virtual_mc_base_address; - - /** Handle of allocated memory to be used by the given process only. */ - amdgpu_bo_handle buf_handle; -}; - -/** * Special UMD specific information associated with buffer. * * It may be need to pass some buffer charactersitic as part @@ -213,13 +209,6 @@ struct amdgpu_bo_info { */ uint64_t phys_alignment; - /** - * Assigned virtual MC Base Address. - * \note This information will be returned only if this buffer was - * allocated in the same process otherwise 0 will be returned. - */ - uint64_t virtual_mc_base_address; - /** Heap where to allocate memory. */ uint32_t preferred_heap; @@ -242,9 +231,6 @@ struct amdgpu_bo_import_result { /** Buffer size */ uint64_t alloc_size; - - /** Assigned virtual MC Base Address */ - uint64_t virtual_mc_base_address; }; /** @@ -266,13 +252,14 @@ struct amdgpu_gds_resource_info { }; /** - * Structure describing CS dependency + * Structure describing CS fence * - * \sa amdgpu_cs_request, amdgpu_cs_submit() + * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() * */ -struct amdgpu_cs_dep_info { - /** Context to which the fence belongs */ +struct amdgpu_cs_fence { + + /** In which context IB was sent to execution */ amdgpu_context_handle context; /** To which HW IP type the fence belongs */ @@ -310,6 +297,20 @@ struct amdgpu_cs_ib_info { }; /** + * Structure describing fence information + * + * \sa amdgpu_cs_request, amdgpu_cs_query_fence, + * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() +*/ +struct amdgpu_cs_fence_info { + /** buffer object for the fence */ + amdgpu_bo_handle handle; + + /** fence offset in the unit of sizeof(uint64_t) */ + uint64_t offset; +}; + +/** * Structure describing submission request * * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx @@ -347,7 +348,7 @@ struct amdgpu_cs_request { * Array of dependencies which need to be met before * execution can start. */ - struct amdgpu_cs_dep_info *dependencies; + struct amdgpu_cs_fence *dependencies; /** Number of IBs to submit in the field ibs. */ uint32_t number_of_ibs; @@ -356,30 +357,16 @@ struct amdgpu_cs_request { * IBs to submit. Those IBs will be submit together as single entity */ struct amdgpu_cs_ib_info *ibs; -}; - -/** - * Structure describing request to check submission state using fence - * - * \sa amdgpu_cs_query_fence_status() - * -*/ -struct amdgpu_cs_query_fence { - /** In which context IB was sent to execution */ - amdgpu_context_handle context; - - /** To which HW IP type the fence belongs */ - unsigned ip_type; - - /** IP instance index if there are several IPs of the same type. */ - unsigned ip_instance; - - /** Ring index of the HW IP */ - uint32_t ring; + /** + * The returned sequence number for the command submission + */ + uint64_t seq_no; - /** Specify fence for which we need to check submission status.*/ - uint64_t fence; + /** + * The fence information + */ + struct amdgpu_cs_fence_info fence_info; }; /** @@ -486,6 +473,10 @@ struct amdgpu_gpu_info { uint32_t vram_bit_width; /** constant engine ram size*/ uint32_t ce_ram_size; + /* vce harvesting instance */ + uint32_t vce_harvest_config; + /* PCI revision ID */ + uint32_t pci_rev_id; }; @@ -557,8 +548,7 @@ int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); * See #amdgpu_device_initialize() * \param alloc_buffer - \c [in] Pointer to the structure describing an * allocation request - * \param info - \c [out] Pointer to structure which return - * information about allocated memory + * \param buf_handle - \c [out] Allocated buffer handle * * \return 0 on success\n * <0 - Negative POSIX Error code @@ -567,7 +557,7 @@ int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); */ int amdgpu_bo_alloc(amdgpu_device_handle dev, struct amdgpu_bo_alloc_request *alloc_buffer, - struct amdgpu_bo_alloc_result *info); + amdgpu_bo_handle *buf_handle); /** * Associate opaque data with buffer to be queried by another UMD @@ -651,7 +641,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev, * want to map to GPU address space (make GPU accessible) * (This address must be correctly aligned). * \param size - [in] Size of allocation (must be correctly aligned) - * \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as + * \param buf_handle - [out] Buffer handle for the userptr memory * resource on submission and be used in other operations. * * @@ -676,7 +666,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev, */ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, void *cpu, uint64_t size, - struct amdgpu_bo_alloc_result *info); + amdgpu_bo_handle *buf_handle); /** * Free previosuly allocated memory @@ -699,7 +689,7 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, int amdgpu_bo_free(amdgpu_bo_handle buf_handle); /** - * Request CPU access to GPU accessable memory + * Request CPU access to GPU accessible memory * * \param buf_handle - \c [in] Buffer handle * \param cpu - \c [out] CPU address to be used for access @@ -728,7 +718,7 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); /** * Wait until a buffer is not used by the device. * - * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize() + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() * \param buf_handle - \c [in] Buffer handle. * \param timeout_ns - Timeout in nanoseconds. * \param buffer_busy - 0 if buffer is idle, all GPU access was completed @@ -864,22 +854,20 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context, * from the same GPU context to the same ip:ip_instance:ring will be executed in * order. * + * The caller can specify the user fence buffer/location with the fence_info in the + * cs_request.The sequence number is returned via the 'seq_no' parameter + * in ibs_request structure. + * * * \param dev - \c [in] Device handle. * See #amdgpu_device_initialize() * \param context - \c [in] GPU Context * \param flags - \c [in] Global submission flags - * \param ibs_request - \c [in] Pointer to submission requests. + * \param ibs_request - \c [in/out] Pointer to submission requests. * We could submit to the several * engines/rings simulteniously as * 'atomic' operation * \param number_of_requests - \c [in] Number of submission requests - * \param fences - \c [out] Pointer to array of data to get - * fences to identify submission - * requests. Timestamps are valid - * in this GPU context and could be used - * to identify/detect completion of - * submission request * * \return 0 on success\n * <0 - Negative POSIX Error code @@ -896,8 +884,7 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context, int amdgpu_cs_submit(amdgpu_context_handle context, uint64_t flags, struct amdgpu_cs_request *ibs_request, - uint32_t number_of_requests, - uint64_t *fences); + uint32_t number_of_requests); /** * Query status of Command Buffer Submission @@ -919,11 +906,34 @@ int amdgpu_cs_submit(amdgpu_context_handle context, * * \sa amdgpu_cs_submit() */ -int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence, +int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, uint64_t timeout_ns, uint64_t flags, uint32_t *expired); +/** + * Wait for multiple fences + * + * \param fences - \c [in] The fence array to wait + * \param fence_count - \c [in] The fence count + * \param wait_all - \c [in] If true, wait all fences to be signaled, + * otherwise, wait at least one fence + * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds + * \param status - \c [out] '1' for signaled, '0' for timeout + * \param first - \c [out] the index of the first signaled fence from @fences + * + * \return 0 on success + * <0 - Negative POSIX Error code + * + * \note Currently it supports only one amdgpu_device. All fences come from + * the same amdgpu_device with the same fd. +*/ +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout_ns, + uint32_t *status, uint32_t *first); + /* * Query / Info API * @@ -1076,6 +1086,24 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, struct amdgpu_gds_resource_info *gds_info); /** + * Query information about sensor. + * + * The return size is query-specific and depends on the "sensor_type" + * parameter. No more than "size" bytes is returned. + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* + * \param size - \c [in] Size of the returned value. + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, + unsigned size, void *value); + +/** * Read a set of consecutive memory-mapped registers. * Not all registers are allowed to be read by userspace. * @@ -1097,6 +1125,11 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, uint32_t *values); /** + * Flag to request VA address range in the 32bit address space +*/ +#define AMDGPU_VA_RANGE_32_BIT 0x1 + +/** * Allocate virtual address range * * \param dev - [in] Device handle. See #amdgpu_device_initialize() @@ -1116,6 +1149,7 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, * \param va_base_allocated - \c [out] On return: Allocated VA base to be used * by client. * \param va_range_handle - \c [out] On return: Handle assigned to allocation + * \param flags - \c [in] flags for special VA range * * \return 0 on success\n * >0 - AMD specific error code\n @@ -1137,7 +1171,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, uint64_t va_base_alignment, uint64_t va_base_required, uint64_t *va_base_allocated, - amdgpu_va_handle *va_range_handle); + amdgpu_va_handle *va_range_handle, + uint64_t flags); /** * Free previously allocated virtual address range @@ -1173,4 +1208,128 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, uint64_t *start, uint64_t *end); +/** + * VA mapping/unmapping for the buffer object + * + * \param bo - \c [in] BO handle + * \param offset - \c [in] Start offset to map + * \param size - \c [in] Size to map + * \param addr - \c [in] Start virtual address. + * \param flags - \c [in] Supported flags for mapping/unmapping + * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ + +int amdgpu_bo_va_op(amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops); + +/** + * VA mapping/unmapping for a buffer object or PRT region. + * + * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all + * parameters are treated "raw", i.e. size is not automatically aligned, and + * all flags must be specified explicitly. + * + * \param dev - \c [in] device handle + * \param bo - \c [in] BO handle (may be NULL) + * \param offset - \c [in] Start offset to map + * \param size - \c [in] Size to map + * \param addr - \c [in] Start virtual address. + * \param flags - \c [in] Supported flags for mapping/unmapping + * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ + +int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops); + +/** + * create semaphore + * + * \param sem - \c [out] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); + +/** + * signal semaphore + * + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [in] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_semaphore_handle sem); + +/** + * wait semaphore + * + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [in] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_semaphore_handle sem); + +/** + * destroy semaphore + * + * \param sem - \c [in] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); + +/** + * Get the ASIC marketing name + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * + * \return the constant string of the marketing name + * "NULL" means the ASIC is not found +*/ +const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); + +#ifdef __cplusplus +} +#endif + #endif /* #ifdef _AMDGPU_H_ */