X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=amdgpu%2Famdgpu.h;h=1901fa8c6867ebb1f067e87705bc99162680046b;hb=41be41f99eb53bd4998b1cd930fa63f0e552d971;hp=06020d96c6d7881ae257727922083b56f0350397;hpb=d2cbe9ecbef8bcfb226986bb2bed508b55dc2999;p=android-x86%2Fexternal-libdrm.git diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 06020d96..1901fa8c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -19,7 +19,7 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * -*/ + */ /** * \file amdgpu.h @@ -37,6 +37,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + struct drm_amdgpu_info_hw_ip; /*--------------------------------------------------------------------------*/ @@ -124,6 +128,11 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; */ typedef struct amdgpu_va *amdgpu_va_handle; +/** + * Define handle for semaphore + */ +typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; + /*--------------------------------------------------------------------------*/ /* -------------------------- Structures ---------------------------------- */ /*--------------------------------------------------------------------------*/ @@ -466,6 +475,8 @@ struct amdgpu_gpu_info { uint32_t ce_ram_size; /* vce harvesting instance */ uint32_t vce_harvest_config; + /* PCI revision ID */ + uint32_t pci_rev_id; }; @@ -678,7 +689,7 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, int amdgpu_bo_free(amdgpu_bo_handle buf_handle); /** - * Request CPU access to GPU accessable memory + * Request CPU access to GPU accessible memory * * \param buf_handle - \c [in] Buffer handle * \param cpu - \c [out] CPU address to be used for access @@ -707,7 +718,7 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); /** * Wait until a buffer is not used by the device. * - * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize() + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() * \param buf_handle - \c [in] Buffer handle. * \param timeout_ns - Timeout in nanoseconds. * \param buffer_busy - 0 if buffer is idle, all GPU access was completed @@ -844,7 +855,7 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context, * order. * * The caller can specify the user fence buffer/location with the fence_info in the - * cs_request.The sequence number is returned via the 'seq_no' paramter + * cs_request.The sequence number is returned via the 'seq_no' parameter * in ibs_request structure. * * @@ -900,6 +911,29 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, uint64_t flags, uint32_t *expired); +/** + * Wait for multiple fences + * + * \param fences - \c [in] The fence array to wait + * \param fence_count - \c [in] The fence count + * \param wait_all - \c [in] If true, wait all fences to be signaled, + * otherwise, wait at least one fence + * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds + * \param status - \c [out] '1' for signaled, '0' for timeout + * \param first - \c [out] the index of the first signaled fence from @fences + * + * \return 0 on success + * <0 - Negative POSIX Error code + * + * \note Currently it supports only one amdgpu_device. All fences come from + * the same amdgpu_device with the same fd. +*/ +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout_ns, + uint32_t *status, uint32_t *first); + /* * Query / Info API * @@ -1052,6 +1086,24 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, struct amdgpu_gds_resource_info *gds_info); /** + * Query information about sensor. + * + * The return size is query-specific and depends on the "sensor_type" + * parameter. No more than "size" bytes is returned. + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* + * \param size - \c [in] Size of the returned value. + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, + unsigned size, void *value); + +/** * Read a set of consecutive memory-mapped registers. * Not all registers are allowed to be read by userspace. * @@ -1073,6 +1125,11 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, uint32_t *values); /** + * Flag to request VA address range in the 32bit address space +*/ +#define AMDGPU_VA_RANGE_32_BIT 0x1 + +/** * Allocate virtual address range * * \param dev - [in] Device handle. See #amdgpu_device_initialize() @@ -1173,4 +1230,106 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, uint64_t flags, uint32_t ops); +/** + * VA mapping/unmapping for a buffer object or PRT region. + * + * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all + * parameters are treated "raw", i.e. size is not automatically aligned, and + * all flags must be specified explicitly. + * + * \param dev - \c [in] device handle + * \param bo - \c [in] BO handle (may be NULL) + * \param offset - \c [in] Start offset to map + * \param size - \c [in] Size to map + * \param addr - \c [in] Start virtual address. + * \param flags - \c [in] Supported flags for mapping/unmapping + * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ + +int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops); + +/** + * create semaphore + * + * \param sem - \c [out] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); + +/** + * signal semaphore + * + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [in] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_semaphore_handle sem); + +/** + * wait semaphore + * + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [in] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_semaphore_handle sem); + +/** + * destroy semaphore + * + * \param sem - \c [in] semaphore handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); + +/** + * Get the ASIC marketing name + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * + * \return the constant string of the marketing name + * "NULL" means the ASIC is not found +*/ +const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); + +#ifdef __cplusplus +} +#endif + #endif /* #ifdef _AMDGPU_H_ */