X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=amdgpu.c;h=1a1f9fc678c6365f5017d5e05a5f23bc9e9fe0e2;hb=02cc8544bd4b8f58356e703b8729e4ca638c5efe;hp=8448968620b091de2d08e9ab711f27f9809fc1ed;hpb=4a4646a5550219de6114311c552e288cb8619840;p=android-x86%2Fexternal-minigbm.git

diff --git a/amdgpu.c b/amdgpu.c
index 8448968..1a1f9fc 100644
--- a/amdgpu.c
+++ b/amdgpu.c
@@ -41,11 +41,11 @@ enum {
 };
 // clang-format on
 
-const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888,
-						  DRM_FORMAT_XRGB8888 };
+const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
+                                                  DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888 };
 
-const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
-						   DRM_FORMAT_NV21, DRM_FORMAT_NV12 };
+const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
+						   DRM_FORMAT_NV12 };
 
 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
 {
@@ -293,7 +293,7 @@ static int amdgpu_init(struct driver *drv)
 
 	metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 	metadata.priority = 2;
-	metadata.modifier = DRM_FORMAT_MOD_NONE;
+	metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 
 	ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 				   &metadata, use_flags);
@@ -306,7 +306,7 @@ static int amdgpu_init(struct driver *drv)
 
 	metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 	metadata.priority = 3;
-	metadata.modifier = DRM_FORMAT_MOD_NONE;
+	metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 
 	ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 				   &metadata, use_flags);
@@ -354,7 +354,6 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint
 	struct amdgpu_bo_metadata metadata = { 0 };
 	ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
 	uint32_t tiling_flags = 0;
-	uint32_t gem_create_flags = 0;
 	size_t plane;
 	int ret;
 
@@ -372,19 +371,13 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint
 		bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
 	}
 
-	if (use_flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
-			 BO_USE_SW_WRITE_OFTEN | BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY))
-		gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-	else
-		gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-
 	memset(&gem_create, 0, sizeof(gem_create));
 
 	gem_create.in.bo_size = bo->total_size;
 	gem_create.in.alignment = addr_out.baseAlign;
 	/* Set the placement. */
 	gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
-	gem_create.in.domain_flags = gem_create_flags;
+	gem_create.in.domain_flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 	/* Allocate the buffer with the preferred heap. */
 	ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 				  sizeof(gem_create));
@@ -402,7 +395,7 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint
 	return ret;
 }
 
-static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot)
+static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
 {
 	int ret;
 	union drm_amdgpu_gem_mmap gem_map;
@@ -415,9 +408,11 @@ static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, i
 		fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 		return MAP_FAILED;
 	}
+
 	data->length = bo->total_size;
 
-	return mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.out.addr_ptr);
+	return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
+		    gem_map.out.addr_ptr);
 }
 
 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)