X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=amdgpu.c;h=7f2abcd379cfbf06724311cf3d4aab58fff98450;hb=662a9fd2acd72fd73e72110924ea9f350429195d;hp=3dce33accb52146917bf05cca901ea672af1c078;hpb=4a3f98cc34b8bfde694c6e1509989637973aff6b;p=android-x86%2Fexternal-minigbm.git diff --git a/amdgpu.c b/amdgpu.c index 3dce33a..7f2abcd 100644 --- a/amdgpu.c +++ b/amdgpu.c @@ -26,6 +26,9 @@ /* DRI backend decides tiling in this case. */ #define TILE_TYPE_DRI 1 +/* Height alignement for Encoder/Decoder buffers */ +#define CHROME_HEIGHT_ALIGN 16 + struct amdgpu_priv { struct dri_driver dri; int drm_version; @@ -44,9 +47,11 @@ struct amdgpu_linear_vma_priv { uint32_t map_flags; }; -const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, - DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888, - DRM_FORMAT_XRGB8888 }; +const static uint32_t render_target_formats[] = { + DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, + DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_ABGR2101010, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR2101010, DRM_FORMAT_XRGB2101010, +}; const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21, DRM_FORMAT_NV12, @@ -361,6 +366,11 @@ static int amdgpu_init(struct driver *drv) drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT); /* @@ -392,6 +402,11 @@ static int amdgpu_init(struct driver *drv) drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); + + drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT); return 0; } @@ -407,16 +422,37 @@ static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t heigh uint64_t use_flags) { int ret; + size_t num_planes; uint32_t plane, stride; - union drm_amdgpu_gem_create gem_create; + union drm_amdgpu_gem_create gem_create = { { 0 } }; struct amdgpu_priv *priv = bo->drv->priv; stride = drv_stride_from_format(format, width, 0); - stride = ALIGN(stride, 256); + num_planes = drv_num_planes_from_format(format); + + /* + * For multiplane formats, align the stride to 512 to ensure that subsample strides are 256 + * aligned. This uses more memory than necessary since the first plane only needs to be + * 256 aligned, but it's acceptable for a short-term fix. It's probably safe for other gpu + * families, but let's restrict it to Raven for now (b/171013552). + * */ + if (priv->dev_info.family == AMDGPU_FAMILY_RV && num_planes > 1) + stride = ALIGN(stride, 512); + else + stride = ALIGN(stride, 256); + + /* + * Currently, allocator used by chrome aligns the height for Encoder/ + * Decoder buffers while allocator used by android(gralloc/minigbm) + * doesn't provide any aligment. + * + * See b/153130069 + */ + if (use_flags & (BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER)) + height = ALIGN(height, CHROME_HEIGHT_ALIGN); drv_bo_from_format(bo, stride, height, format); - memset(&gem_create, 0, sizeof(gem_create)); gem_create.in.bo_size = ALIGN(bo->meta.total_size, priv->dev_info.virtual_address_alignment); gem_create.in.alignment = 256; @@ -426,7 +462,11 @@ static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t heigh gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; - if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT))) + + /* Scanout in GTT requires USWC, otherwise try to use cachable memory + * for buffers that are read often, because uncacheable reads can be + * very slow. USWC should be faster on the GPU though. */ + if ((use_flags & BO_USE_SCANOUT) || !(use_flags & BO_USE_SW_READ_OFTEN)) gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; /* Allocate the buffer with the preferred heap. */ @@ -526,7 +566,7 @@ static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_ { void *addr = MAP_FAILED; int ret; - union drm_amdgpu_gem_mmap gem_map; + union drm_amdgpu_gem_mmap gem_map = { { 0 } }; struct drm_amdgpu_gem_create_in bo_info = { 0 }; struct drm_amdgpu_gem_op gem_op = { 0 }; uint32_t handle = bo->handles[plane].u32; @@ -579,9 +619,7 @@ static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_ } } - memset(&gem_map, 0, sizeof(gem_map)); gem_map.in.handle = handle; - ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); if (ret) { drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); @@ -634,15 +672,23 @@ static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma) } } +static int amdgpu_bo_get_plane_fd(struct bo *bo, size_t plane) +{ + if (bo->priv) + dri_bo_get_plane_fd(bo, plane); + else + /* Fallback to default implementation */ + return -1; +} + static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping) { int ret; - union drm_amdgpu_gem_wait_idle wait_idle; + union drm_amdgpu_gem_wait_idle wait_idle = { { 0 } }; if (bo->priv) return 0; - memset(&wait_idle, 0, sizeof(wait_idle)); wait_idle.in.handle = bo->handles[0].u32; wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE; @@ -686,6 +732,7 @@ const struct backend backend_amdgpu = { .bo_import = amdgpu_import_bo, .bo_map = amdgpu_map_bo, .bo_unmap = amdgpu_unmap_bo, + .bo_get_plane_fd = amdgpu_bo_get_plane_fd, .bo_invalidate = amdgpu_bo_invalidate, .resolve_format = amdgpu_resolve_format, .num_planes_from_modifier = dri_num_planes_from_modifier,