X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=amdgpu.c;h=f6c054763aeeb2ec8255978f810046bdf5d7036e;hb=23e006a90b51589a7515a66777477398ee20c576;hp=1fd9d13d0341eb22a46d9e60661533b9ce3da913;hpb=1b1d56ae4018eaed1da9d6e7032554156b7be020;p=android-x86%2Fexternal-minigbm.git diff --git a/amdgpu.c b/amdgpu.c index 1fd9d13..f6c0547 100644 --- a/amdgpu.c +++ b/amdgpu.c @@ -41,8 +41,12 @@ enum { }; // clang-format on -const static uint32_t supported_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_XRGB8888 }; +const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888 }; + +const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21, + DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID }; static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info) { @@ -133,7 +137,7 @@ static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in) } static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format, - uint32_t usage, uint32_t *tiling_flags, + uint64_t use_flags, uint32_t *tiling_flags, ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out) { ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 }; @@ -145,7 +149,8 @@ static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height /* Set the requested tiling mode. */ addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1; - if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN)) + if (use_flags & + (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN)) addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED; else if (width <= 16 || height <= 16) addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1; @@ -164,7 +169,7 @@ static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height addr_surf_info_in.flags.noStencil = 1; /* Set the micro tile type. */ - if (usage & BO_USE_SCANOUT) + if (use_flags & BO_USE_SCANOUT) addr_surf_info_in.tileType = ADDR_DISPLAYABLE; else addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE; @@ -268,10 +273,9 @@ static void *amdgpu_addrlib_init(int fd) static int amdgpu_init(struct driver *drv) { - int ret; void *addrlib; struct format_metadata metadata; - uint32_t flags = BO_COMMON_USE_MASK; + uint64_t use_flags = BO_USE_RENDER_MASK; addrlib = amdgpu_addrlib_init(drv_get_fd(drv)); if (!addrlib) @@ -279,53 +283,61 @@ static int amdgpu_init(struct driver *drv) drv->priv = addrlib; + drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), + &LINEAR_METADATA, BO_USE_TEXTURE_MASK); + + /* YUV format for camera */ + drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, + BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); + /* + * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots + * from camera. + */ + drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA, + BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); + + drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT); + drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT); + metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED; - metadata.priority = 1; - metadata.modifier = DRM_FORMAT_MOD_NONE; + metadata.priority = 2; + metadata.modifier = DRM_FORMAT_MOD_LINEAR; - ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata, - flags); - if (ret) - return ret; + drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), + &metadata, use_flags); drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED; - metadata.priority = 2; - metadata.modifier = DRM_FORMAT_MOD_NONE; + metadata.priority = 3; + metadata.modifier = DRM_FORMAT_MOD_LINEAR; - ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata, - flags); - if (ret) - return ret; + drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), + &metadata, use_flags); - flags &= ~BO_USE_SW_WRITE_OFTEN; - flags &= ~BO_USE_SW_READ_OFTEN; - flags &= ~BO_USE_LINEAR; + use_flags &= ~BO_USE_SW_WRITE_OFTEN; + use_flags &= ~BO_USE_SW_READ_OFTEN; + use_flags &= ~BO_USE_LINEAR; metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1; - metadata.priority = 3; + metadata.priority = 4; - ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata, - flags); - if (ret) - return ret; + drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), + &metadata, use_flags); drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1; - metadata.priority = 4; + metadata.priority = 5; - ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata, - flags); - if (ret) - return ret; + drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), + &metadata, use_flags); - return ret; + return 0; } static void amdgpu_close(struct driver *drv) @@ -335,36 +347,50 @@ static void amdgpu_close(struct driver *drv) } static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, - uint32_t usage) + uint64_t use_flags) { void *addrlib = bo->drv->priv; union drm_amdgpu_gem_create gem_create; struct amdgpu_bo_metadata metadata = { 0 }; ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 }; uint32_t tiling_flags = 0; - uint32_t gem_create_flags = 0; + size_t plane; int ret; - if (amdgpu_addrlib_compute(addrlib, width, height, format, usage, &tiling_flags, - &addr_out) < 0) - return -EINVAL; - - bo->tiling = tiling_flags; - bo->offsets[0] = 0; - bo->sizes[0] = addr_out.surfSize; - bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8); - if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | - BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY)) - gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - else - gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; + if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) { + drv_bo_from_format(bo, ALIGN(width, 64), height, format); + } else if (format == DRM_FORMAT_YVU420_ANDROID) { + drv_bo_from_format(bo, ALIGN(width, 128), height, format); + } else { + if (amdgpu_addrlib_compute(addrlib, width, height, format, use_flags, &tiling_flags, + &addr_out) < 0) + return -EINVAL; + + bo->tiling = tiling_flags; + /* RGB has 1 plane only */ + bo->offsets[0] = 0; + bo->total_size = bo->sizes[0] = addr_out.surfSize; + bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8); + } memset(&gem_create, 0, sizeof(gem_create)); - gem_create.in.bo_size = bo->sizes[0]; + + gem_create.in.bo_size = bo->total_size; gem_create.in.alignment = addr_out.baseAlign; /* Set the placement. */ - gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM; - gem_create.in.domain_flags = gem_create_flags; + + gem_create.in.domain_flags = 0; + if (use_flags & (BO_USE_LINEAR | BO_USE_SW)) + gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + + if (use_flags & (BO_USE_SCANOUT | BO_USE_CURSOR)) { + /* TODO(dbehr) do not use VRAM after we enable display VM */ + gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM; + } else { + gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; + if (!(use_flags & BO_USE_SW_READ_OFTEN)) + gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; + } /* Allocate the buffer with the preferred heap. */ ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create, @@ -373,35 +399,53 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint if (ret < 0) return ret; - bo->handles[0].u32 = gem_create.out.handle; - metadata.tiling_info = tiling_flags; + for (plane = 0; plane < bo->num_planes; plane++) + bo->handles[plane].u32 = gem_create.out.handle; + ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata); return ret; } -static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane) +static void *amdgpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) { int ret; union drm_amdgpu_gem_mmap gem_map; memset(&gem_map, 0, sizeof(gem_map)); - gem_map.in.handle = bo->handles[0].u32; + gem_map.in.handle = bo->handles[plane].u32; ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); if (ret) { fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); return MAP_FAILED; } - data->length = bo->sizes[0]; - return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd, + vma->length = bo->total_size; + + return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, gem_map.out.addr_ptr); } -struct backend backend_amdgpu = { +static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags) +{ + switch (format) { + case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: + /* Camera subsystem requires NV12. */ + if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) + return DRM_FORMAT_NV12; + /*HACK: See b/28671744 */ + return DRM_FORMAT_XBGR8888; + case DRM_FORMAT_FLEX_YCbCr_420_888: + return DRM_FORMAT_NV12; + default: + return format; + } +} + +const struct backend backend_amdgpu = { .name = "amdgpu", .init = amdgpu_init, .close = amdgpu_close, @@ -409,6 +453,8 @@ struct backend backend_amdgpu = { .bo_destroy = drv_gem_bo_destroy, .bo_import = drv_prime_bo_import, .bo_map = amdgpu_bo_map, + .bo_unmap = drv_bo_munmap, + .resolve_format = amdgpu_resolve_format, }; #endif