X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=i915.c;h=da4de964aa7047db4b14aad09d9546288f7076b7;hb=bbba9dde65832cf03f1a0e9739e81e8ad689a508;hp=43e72c2d9b9305cbeae533b551c05c15ff06bcaa;hpb=39eb9519d751f4b4bb0342028937cfa05b2f43ac;p=android-x86%2Fexternal-minigbm.git diff --git a/i915.c b/i915.c index 43e72c2..da4de96 100644 --- a/i915.c +++ b/i915.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "drv_priv.h" @@ -22,188 +23,151 @@ #define I915_CACHELINE_SIZE 64 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1) -static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555, - DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, - DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010, - DRM_FORMAT_XRGB8888 }; +static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010, + DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XRGB8888 }; -static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, - DRM_FORMAT_UYVY, DRM_FORMAT_YUYV }; +static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F }; -static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID, - DRM_FORMAT_NV12 }; +static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010, + DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID }; + +static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR }; + +static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS, + I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR }; + +struct modifier_support_t { + const uint64_t *order; + uint32_t count; +}; struct i915_device { uint32_t gen; int32_t has_llc; + struct modifier_support_t modifier; }; static uint32_t i915_get_gen(int device_id) { const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE, 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 }; + const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 }; + const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, + 0x9A70, 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, + 0x9AF8 }; unsigned i; for (i = 0; i < ARRAY_SIZE(gen3_ids); i++) if (gen3_ids[i] == device_id) return 3; + /* Gen 11 */ + for (i = 0; i < ARRAY_SIZE(gen11_ids); i++) + if (gen11_ids[i] == device_id) + return 11; + + /* Gen 12 */ + for (i = 0; i < ARRAY_SIZE(gen12_ids); i++) + if (gen12_ids[i] == device_id) + return 12; return 4; } -/* - * We allow allocation of ARGB formats for SCANOUT if the corresponding XRGB - * formats supports it. It's up to the caller (chrome ozone) to ultimately not - * scan out ARGB if the display controller only supports XRGB, but we'll allow - * the allocation of the bo here. - */ -static bool format_compatible(const struct combination *combo, uint32_t format) +static void i915_get_modifier_order(struct i915_device *i915) { - if (combo->format == format) - return true; - - switch (format) { - case DRM_FORMAT_XRGB8888: - return combo->format == DRM_FORMAT_ARGB8888; - case DRM_FORMAT_XBGR8888: - return combo->format == DRM_FORMAT_ABGR8888; - case DRM_FORMAT_RGBX8888: - return combo->format == DRM_FORMAT_RGBA8888; - case DRM_FORMAT_BGRX8888: - return combo->format == DRM_FORMAT_BGRA8888; - default: - return false; + if (i915->gen == 11) { + i915->modifier.order = gen11_modifier_order; + i915->modifier.count = ARRAY_SIZE(gen11_modifier_order); + } else { + i915->modifier.order = gen_modifier_order; + i915->modifier.count = ARRAY_SIZE(gen_modifier_order); } } -static int i915_add_kms_item(struct driver *drv, const struct kms_item *item) +static uint64_t unset_flags(uint64_t current_flags, uint64_t mask) { - uint32_t i; - struct combination *combo; - - /* - * Older hardware can't scanout Y-tiled formats. Newer devices can, and - * report this functionality via format modifiers. - */ - for (i = 0; i < drv_array_size(drv->combos); i++) { - combo = (struct combination *)drv_array_at_idx(drv->combos, i); - if (!format_compatible(combo, item->format)) - continue; - - if (item->modifier == DRM_FORMAT_MOD_LINEAR && - combo->metadata.tiling == I915_TILING_X) { - /* - * FIXME: drv_query_kms() does not report the available modifiers - * yet, but we know that all hardware can scanout from X-tiled - * buffers, so let's add this to our combinations, except for - * cursor, which must not be tiled. - */ - combo->use_flags |= item->use_flags & ~BO_USE_CURSOR; - } - - /* If we can scanout NV12, we support all tiling modes. */ - if (item->format == DRM_FORMAT_NV12) - combo->use_flags |= item->use_flags; - - if (combo->metadata.modifier == item->modifier) - combo->use_flags |= item->use_flags; - } - - return 0; + uint64_t value = current_flags & ~mask; + return value; } static int i915_add_combinations(struct driver *drv) { - int ret; - uint32_t i; - struct drv_array *kms_items; struct format_metadata metadata; - uint64_t render_use_flags, texture_use_flags; + uint64_t render, scanout_and_render, texture_only; - render_use_flags = BO_USE_RENDER_MASK; - texture_use_flags = BO_USE_TEXTURE_MASK; + scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT; + render = BO_USE_RENDER_MASK; + texture_only = BO_USE_TEXTURE_MASK; + uint64_t linear_mask = + BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN; metadata.tiling = I915_TILING_NONE; metadata.priority = 1; metadata.modifier = DRM_FORMAT_MOD_LINEAR; - drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, render_use_flags); + drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats), + &metadata, scanout_and_render); - drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), - &metadata, texture_use_flags); + drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render); - drv_add_combinations(drv, tileable_texture_source_formats, - ARRAY_SIZE(tileable_texture_source_formats), &metadata, - texture_use_flags); + drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata, + texture_only); - /* Android CTS tests require this. */ - drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); - - drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); - drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); + drv_modify_linear_combinations(drv); + /* NV12 format for camera, display, decoding and encoding. */ /* IPU3 camera ISP supports only NV12 output. */ drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, - BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); + BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT | + BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER); + + /* Android CTS tests require this. */ + drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); + /* * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots - * from camera. + * from camera and input/output from hardware decoder/encoder. */ drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, - BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); + BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER | + BO_USE_HW_VIDEO_ENCODER); - render_use_flags &= ~BO_USE_RENDERSCRIPT; - render_use_flags &= ~BO_USE_SW_WRITE_OFTEN; - render_use_flags &= ~BO_USE_SW_READ_OFTEN; - render_use_flags &= ~BO_USE_LINEAR; - render_use_flags &= ~BO_USE_PROTECTED; - - texture_use_flags &= ~BO_USE_RENDERSCRIPT; - texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN; - texture_use_flags &= ~BO_USE_SW_READ_OFTEN; - texture_use_flags &= ~BO_USE_LINEAR; - texture_use_flags &= ~BO_USE_PROTECTED; + render = unset_flags(render, linear_mask); + scanout_and_render = unset_flags(scanout_and_render, linear_mask); metadata.tiling = I915_TILING_X; metadata.priority = 2; metadata.modifier = I915_FORMAT_MOD_X_TILED; - drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, render_use_flags); - - drv_add_combinations(drv, tileable_texture_source_formats, - ARRAY_SIZE(tileable_texture_source_formats), &metadata, - texture_use_flags); + drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render); + drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats), + &metadata, scanout_and_render); metadata.tiling = I915_TILING_Y; metadata.priority = 3; metadata.modifier = I915_FORMAT_MOD_Y_TILED; - drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, render_use_flags); - - drv_add_combinations(drv, tileable_texture_source_formats, - ARRAY_SIZE(tileable_texture_source_formats), &metadata, - texture_use_flags); - - /* Support y-tiled NV12 for libva */ + scanout_and_render = + unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY); +/* Support y-tiled NV12 and P010 for libva */ +#ifdef I915_SCANOUT_Y_TILED + drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, + BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT); +#else drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER); +#endif + scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT); + drv_add_combination(drv, DRM_FORMAT_P010, &metadata, + BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER); - kms_items = drv_query_kms(drv); - if (!kms_items) - return 0; - - for (i = 0; i < drv_array_size(kms_items); i++) { - ret = i915_add_kms_item(drv, (struct kms_item *)drv_array_at_idx(kms_items, i)); - if (ret) { - drv_array_destroy(kms_items); - return ret; - } - } - - drv_array_destroy(kms_items); + drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render); + drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats), + &metadata, scanout_and_render); return 0; } @@ -244,7 +208,7 @@ static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *strid break; } - *aligned_height = ALIGN(bo->height, vertical_alignment); + *aligned_height = ALIGN(*aligned_height, vertical_alignment); if (i915->gen > 3) { *stride = ALIGN(*stride, horizontal_alignment); } else { @@ -277,13 +241,12 @@ static int i915_init(struct driver *drv) int ret; int device_id; struct i915_device *i915; - drm_i915_getparam_t get_param; + drm_i915_getparam_t get_param = { 0 }; i915 = calloc(1, sizeof(*i915)); if (!i915) return -ENOMEM; - memset(&get_param, 0, sizeof(get_param)); get_param.param = I915_PARAM_CHIPSET_ID; get_param.value = &device_id; ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); @@ -294,6 +257,7 @@ static int i915_init(struct driver *drv) } i915->gen = i915_get_gen(device_id); + i915_get_modifier_order(i915); memset(&get_param, 0, sizeof(get_param)); get_param.param = I915_PARAM_HAS_LLC; @@ -314,52 +278,78 @@ static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, u { uint32_t offset; size_t plane; - int ret; + int ret, pagesize; offset = 0; + pagesize = getpagesize(); for (plane = 0; plane < drv_num_planes_from_format(format); plane++) { uint32_t stride = drv_stride_from_format(format, width, plane); uint32_t plane_height = drv_height_from_format(format, height, plane); - if (bo->tiling != I915_TILING_NONE) - assert(IS_ALIGNED(offset, 4096)); + if (bo->meta.tiling != I915_TILING_NONE) + assert(IS_ALIGNED(offset, pagesize)); - ret = i915_align_dimensions(bo, bo->tiling, &stride, &plane_height); + ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height); if (ret) return ret; - bo->strides[plane] = stride; - bo->sizes[plane] = stride * plane_height; - bo->offsets[plane] = offset; - offset += bo->sizes[plane]; + bo->meta.strides[plane] = stride; + bo->meta.sizes[plane] = stride * plane_height; + bo->meta.offsets[plane] = offset; + offset += bo->meta.sizes[plane]; } - bo->total_size = offset; + bo->meta.total_size = ALIGN(offset, pagesize); return 0; } -static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height, - uint32_t format, uint64_t modifier) +static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, + uint64_t use_flags, const uint64_t *modifiers, uint32_t count) { - int ret; - size_t plane; - struct drm_i915_gem_create gem_create; - struct drm_i915_gem_set_tiling gem_set_tiling; + uint64_t modifier; + struct i915_device *i915 = bo->drv->priv; + bool huge_bo = (i915->gen <= 11) && (width > 4096); + + if (modifiers) { + modifier = + drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count); + } else { + struct combination *combo = drv_get_combination(bo->drv, format, use_flags); + if (!combo) + return -EINVAL; + modifier = combo->metadata.modifier; + } + + /* + * i915 only supports linear/x-tiled above 4096 wide + */ + if (huge_bo && modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) { + uint32_t i; + for (i = 0; modifiers && i < count; i++) { + if (modifiers[i] == I915_FORMAT_MOD_X_TILED) + break; + } + if (i == count) + modifier = DRM_FORMAT_MOD_LINEAR; + else + modifier = I915_FORMAT_MOD_X_TILED; + } switch (modifier) { case DRM_FORMAT_MOD_LINEAR: - bo->tiling = I915_TILING_NONE; + bo->meta.tiling = I915_TILING_NONE; break; case I915_FORMAT_MOD_X_TILED: - bo->tiling = I915_TILING_X; + bo->meta.tiling = I915_TILING_X; break; case I915_FORMAT_MOD_Y_TILED: - bo->tiling = I915_TILING_Y; + case I915_FORMAT_MOD_Y_TILED_CCS: + bo->meta.tiling = I915_TILING_Y; break; } - bo->format_modifiers[0] = modifier; + bo->meta.format_modifiers[0] = modifier; if (format == DRM_FORMAT_YVU420_ANDROID) { /* @@ -372,31 +362,77 @@ static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t h */ uint32_t stride = ALIGN(width, 32); drv_bo_from_format(bo, stride, height, format); + } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) { + /* + * For compressed surfaces, we need a color control surface + * (CCS). Color compression is only supported for Y tiled + * surfaces, and for each 32x16 tiles in the main surface we + * need a tile in the control surface. Y tiles are 128 bytes + * wide and 32 lines tall and we use that to first compute the + * width and height in tiles of the main surface. stride and + * height are already multiples of 128 and 32, respectively: + */ + uint32_t stride = drv_stride_from_format(format, width, 0); + uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128); + uint32_t height_in_tiles = DIV_ROUND_UP(height, 32); + uint32_t size = width_in_tiles * height_in_tiles * 4096; + uint32_t offset = 0; + + bo->meta.strides[0] = width_in_tiles * 128; + bo->meta.sizes[0] = size; + bo->meta.offsets[0] = offset; + offset += size; + + /* + * Now, compute the width and height in tiles of the control + * surface by dividing and rounding up. + */ + uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32); + uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16); + uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096; + + /* + * With stride and height aligned to y tiles, offset is + * already a multiple of 4096, which is the required alignment + * of the CCS. + */ + bo->meta.strides[1] = ccs_width_in_tiles * 128; + bo->meta.sizes[1] = ccs_size; + bo->meta.offsets[1] = offset; + offset += ccs_size; + + bo->meta.num_planes = 2; + bo->meta.total_size = offset; } else { i915_bo_from_format(bo, width, height, format); } + return 0; +} - memset(&gem_create, 0, sizeof(gem_create)); - gem_create.size = bo->total_size; +static int i915_bo_create_from_metadata(struct bo *bo) +{ + int ret; + size_t plane; + struct drm_i915_gem_create gem_create = { 0 }; + struct drm_i915_gem_set_tiling gem_set_tiling = { 0 }; + gem_create.size = bo->meta.total_size; ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create); if (ret) { drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size); - return ret; + return -errno; } - for (plane = 0; plane < bo->num_planes; plane++) + for (plane = 0; plane < bo->meta.num_planes; plane++) bo->handles[plane].u32 = gem_create.handle; - memset(&gem_set_tiling, 0, sizeof(gem_set_tiling)); gem_set_tiling.handle = bo->handles[0].u32; - gem_set_tiling.tiling_mode = bo->tiling; - gem_set_tiling.stride = bo->strides[0]; + gem_set_tiling.tiling_mode = bo->meta.tiling; + gem_set_tiling.stride = bo->meta.strides[0]; ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling); if (ret) { - struct drm_gem_close gem_close; - memset(&gem_close, 0, sizeof(gem_close)); + struct drm_gem_close gem_close = { 0 }; gem_close.handle = bo->handles[0].u32; drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close); @@ -407,33 +443,6 @@ static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t h return 0; } -static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, - uint64_t use_flags) -{ - struct combination *combo; - - combo = drv_get_combination(bo->drv, format, use_flags); - if (!combo) - return -EINVAL; - - return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier); -} - -static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height, - uint32_t format, const uint64_t *modifiers, uint32_t count) -{ - static const uint64_t modifier_order[] = { - I915_FORMAT_MOD_Y_TILED, - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - }; - uint64_t modifier; - - modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order)); - - return i915_bo_create_for_modifier(bo, width, height, format, modifier); -} - static void i915_close(struct driver *drv) { free(drv->priv); @@ -443,14 +452,13 @@ static void i915_close(struct driver *drv) static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data) { int ret; - struct drm_i915_gem_get_tiling gem_get_tiling; + struct drm_i915_gem_get_tiling gem_get_tiling = { 0 }; ret = drv_prime_bo_import(bo, data); if (ret) return ret; /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */ - memset(&gem_get_tiling, 0, sizeof(gem_get_tiling)); gem_get_tiling.handle = bo->handles[0].u32; ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling); @@ -460,7 +468,7 @@ static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data) return ret; } - bo->tiling = gem_get_tiling.tiling_mode; + bo->meta.tiling = gem_get_tiling.tiling_mode; return 0; } @@ -469,10 +477,11 @@ static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t int ret; void *addr; - if (bo->tiling == I915_TILING_NONE) { - struct drm_i915_gem_mmap gem_map; - memset(&gem_map, 0, sizeof(gem_map)); + if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS) + return MAP_FAILED; + if (bo->meta.tiling == I915_TILING_NONE) { + struct drm_i915_gem_mmap gem_map = { 0 }; /* TODO(b/118799155): We don't seem to have a good way to * detect the use cases for which WC mapping is really needed. * The current heuristic seems overly coarse and may be slowing @@ -481,14 +490,14 @@ static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t * For now, care must be taken not to use WC mappings for * Renderscript and camera use cases, as they're * performance-sensitive. */ - if ((bo->use_flags & BO_USE_SCANOUT) && - !(bo->use_flags & + if ((bo->meta.use_flags & BO_USE_SCANOUT) && + !(bo->meta.use_flags & (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))) gem_map.flags = I915_MMAP_WC; gem_map.handle = bo->handles[0].u32; gem_map.offset = 0; - gem_map.size = bo->total_size; + gem_map.size = bo->meta.total_size; ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map); if (ret) { @@ -498,19 +507,17 @@ static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t addr = (void *)(uintptr_t)gem_map.addr_ptr; } else { - struct drm_i915_gem_mmap_gtt gem_map; - memset(&gem_map, 0, sizeof(gem_map)); + struct drm_i915_gem_mmap_gtt gem_map = { 0 }; gem_map.handle = bo->handles[0].u32; - ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map); if (ret) { drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n"); return MAP_FAILED; } - addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, - gem_map.offset); + addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, + bo->drv->fd, gem_map.offset); } if (addr == MAP_FAILED) { @@ -518,18 +525,17 @@ static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t return addr; } - vma->length = bo->total_size; + vma->length = bo->meta.total_size; return addr; } static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping) { int ret; - struct drm_i915_gem_set_domain set_domain; + struct drm_i915_gem_set_domain set_domain = { 0 }; - memset(&set_domain, 0, sizeof(set_domain)); set_domain.handle = bo->handles[0].u32; - if (bo->tiling == I915_TILING_NONE) { + if (bo->meta.tiling == I915_TILING_NONE) { set_domain.read_domains = I915_GEM_DOMAIN_CPU; if (mapping->vma->map_flags & BO_MAP_WRITE) set_domain.write_domain = I915_GEM_DOMAIN_CPU; @@ -551,13 +557,13 @@ static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping) static int i915_bo_flush(struct bo *bo, struct mapping *mapping) { struct i915_device *i915 = bo->drv->priv; - if (!i915->has_llc && bo->tiling == I915_TILING_NONE) + if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE) i915_clflush(mapping->vma->addr, mapping->vma->length); return 0; } -static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags) +static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags) { switch (format) { case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: @@ -586,8 +592,8 @@ const struct backend backend_i915 = { .name = "i915", .init = i915_init, .close = i915_close, - .bo_create = i915_bo_create, - .bo_create_with_modifiers = i915_bo_create_with_modifiers, + .bo_compute_metadata = i915_bo_compute_metadata, + .bo_create_from_metadata = i915_bo_create_from_metadata, .bo_destroy = drv_gem_bo_destroy, .bo_import = i915_bo_import, .bo_map = i915_bo_map,