X-Git-Url: http://git.osdn.net/view?a=blobdiff_plain;f=tegra.c;h=d16a182e84d433441a57a855100135b306d06a33;hb=9dea0f87c5526e2bd649afbb7abd3e54572e76f0;hp=7ddeb96873c53f7fc15c09cdbfc7660c0a9c665e;hpb=657058557680c8c8ed12e166046b394460199c3d;p=android-x86%2Fexternal-minigbm.git diff --git a/tegra.c b/tegra.c index 7ddeb96..d16a182 100644 --- a/tegra.c +++ b/tegra.c @@ -44,7 +44,6 @@ enum tegra_map_type { struct tegra_private_map_data { void *tiled; void *untiled; - int prot; }; static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888 }; @@ -182,29 +181,29 @@ static int tegra_init(struct driver *drv) { int ret; struct format_metadata metadata; - uint64_t flags = BO_USE_RENDER_MASK; + uint64_t use_flags = BO_USE_RENDER_MASK; metadata.tiling = NV_MEM_KIND_PITCH; metadata.priority = 1; - metadata.modifier = DRM_FORMAT_MOD_NONE; + metadata.modifier = DRM_FORMAT_MOD_LINEAR; ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, flags); + &metadata, use_flags); if (ret) return ret; drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); - flags &= ~BO_USE_SW_WRITE_OFTEN; - flags &= ~BO_USE_SW_READ_OFTEN; - flags &= ~BO_USE_LINEAR; + use_flags &= ~BO_USE_SW_WRITE_OFTEN; + use_flags &= ~BO_USE_SW_READ_OFTEN; + use_flags &= ~BO_USE_LINEAR; metadata.tiling = NV_MEM_KIND_C32_2CRA; metadata.priority = 2; ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), - &metadata, flags); + &metadata, use_flags); if (ret) return ret; @@ -214,14 +213,15 @@ static int tegra_init(struct driver *drv) } static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, - uint32_t flags) + uint64_t use_flags) { uint32_t size, stride, block_height_log2 = 0; enum nv_mem_kind kind = NV_MEM_KIND_PITCH; struct drm_tegra_gem_create gem_create; int ret; - if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN)) + if (use_flags & + (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN)) compute_layout_linear(width, height, format, &stride, &size); else compute_layout_blocklinear(width, height, format, &kind, &block_height_log2, @@ -265,7 +265,42 @@ static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint3 return 0; } -static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot) +static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data) +{ + int ret; + struct drm_tegra_gem_get_tiling gem_get_tiling; + + ret = drv_prime_bo_import(bo, data); + if (ret) + return ret; + + /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */ + memset(&gem_get_tiling, 0, sizeof(gem_get_tiling)); + gem_get_tiling.handle = bo->handles[0].u32; + + ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling); + if (ret) { + drv_gem_bo_destroy(bo); + return ret; + } + + /* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are + tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */ + if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) { + bo->tiling = NV_MEM_KIND_PITCH; + } else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) { + bo->tiling = NV_MEM_KIND_C32_2CRA; + } else { + fprintf(stderr, "tegra_bo_import: unknown tile format %d", gem_get_tiling.mode); + drv_gem_bo_destroy(bo); + assert(0); + } + + bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling); + return 0; +} + +static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags) { int ret; struct drm_tegra_gem_mmap gem_map; @@ -280,13 +315,13 @@ static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane, in return MAP_FAILED; } - void *addr = mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.offset); + void *addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, + gem_map.offset); data->length = bo->total_size; if ((bo->tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) { priv = calloc(1, sizeof(*priv)); priv->untiled = calloc(1, bo->total_size); priv->tiled = addr; - priv->prot = prot; data->priv = priv; transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_READ_TILED_BUFFER); addr = priv->untiled; @@ -299,9 +334,6 @@ static int tegra_bo_unmap(struct bo *bo, struct map_info *data) { if (data->priv) { struct tegra_private_map_data *priv = data->priv; - if (priv->prot & PROT_WRITE) - transfer_tiled_memory(bo, priv->tiled, priv->untiled, - TEGRA_WRITE_TILED_BUFFER); data->addr = priv->tiled; free(priv->untiled); free(priv); @@ -311,38 +343,13 @@ static int tegra_bo_unmap(struct bo *bo, struct map_info *data) return munmap(data->addr, data->length); } -static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data) +static int tegra_bo_flush(struct bo *bo, struct map_info *data) { - int ret; - struct drm_tegra_gem_get_tiling gem_get_tiling; - - ret = drv_prime_bo_import(bo, data); - if (ret) - return ret; - - /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */ - memset(&gem_get_tiling, 0, sizeof(gem_get_tiling)); - gem_get_tiling.handle = bo->handles[0].u32; - - ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling); - if (ret) { - drv_gem_bo_destroy(bo); - return ret; - } + struct tegra_private_map_data *priv = data->priv; - /* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are - tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */ - if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) { - bo->tiling = NV_MEM_KIND_PITCH; - } else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) { - bo->tiling = NV_MEM_KIND_C32_2CRA; - } else { - fprintf(stderr, "tegra_bo_import: unknown tile format %d", gem_get_tiling.mode); - drv_gem_bo_destroy(bo); - assert(0); - } + if (priv && (data->map_flags & BO_MAP_WRITE)) + transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_WRITE_TILED_BUFFER); - bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling); return 0; } @@ -354,6 +361,7 @@ struct backend backend_tegra = { .bo_import = tegra_bo_import, .bo_map = tegra_bo_map, .bo_unmap = tegra_bo_unmap, + .bo_flush = tegra_bo_flush, }; #endif