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[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.
authorCraig Topper <craig.topper@intel.com>
Tue, 20 Mar 2018 03:01:59 +0000 (03:01 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 20 Mar 2018 03:01:59 +0000 (03:01 +0000)
commit001a48c5f666b9cc06fd5841a2b85419d1a436e0
tree05aae81cf3b5e031d8ff768ae662bc3f2322529ctree | snapshot
parentc83d754ae2b43bd61b741f319d7fd343ec1c0a07commit | diff
[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.

I assume these match the generic immediate version like they do in the other models.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327943 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86SchedSandyBridge.td diff | blob | history
test/CodeGen/X86/schedule-x86_64.ll diff | blob | history
external/llvm
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