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[RISCV] Improve scalable-vector shift tests (NFC)
authorFraser Cormack <fraser@codeplay.com>
Fri, 8 Jan 2021 17:14:08 +0000 (17:14 +0000)
committerFraser Cormack <fraser@codeplay.com>
Tue, 12 Jan 2021 11:40:21 +0000 (11:40 +0000)
commit09db958e37b3a51942827a48a4b2f453e8fb4737
tree121582bdc4ee8a46d8956af05863e2f53ed90981tree | snapshot
parentace516fb33d1f3de85f046e96efc1048b4ee8c08commit | diff
[RISCV] Improve scalable-vector shift tests (NFC)

All i8/i16 and several i32 tests were testing immediate shift amounts
which exceeded the bits in the vector elements, creating poison values.
Amend the tests to test well-behaved shift amounts.
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll diff | blob | history
external/llvm-project
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