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AMDGPU: Fix unnecessary ands when packing f16 vectors
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 15 Mar 2017 19:04:26 +0000 (19:04 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 15 Mar 2017 19:04:26 +0000 (19:04 +0000)
commit0c52bece0127f156bc5198f84bcbed3fc236c739
tree1a8de5e2de252461c5ac0ca55b9c1290192506f3
parentf4523b0efd797e6f9f147129bc404fedecf18ebf
AMDGPU: Fix unnecessary ands when packing f16 vectors

computeKnownBits didn't handle fp_to_fp16 to report
the high bits as 0. ARM maps the generic node to an instruction
that does not modify the high bits of the register, so introduce
a target node where the high bits are known 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297873 91177308-0d34-0410-b5e6-96231b3b80d8
29 files changed:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
lib/Target/AMDGPU/AMDGPUISelLowering.h
lib/Target/AMDGPU/AMDGPUInstrInfo.td
lib/Target/AMDGPU/EvergreenInstructions.td
lib/Target/AMDGPU/SIInstructions.td
lib/Target/AMDGPU/VOP1Instructions.td
test/CodeGen/AMDGPU/fabs.f16.ll
test/CodeGen/AMDGPU/fadd.f16.ll
test/CodeGen/AMDGPU/fmul.f16.ll
test/CodeGen/AMDGPU/fptrunc.f16.ll
test/CodeGen/AMDGPU/fsub.f16.ll
test/CodeGen/AMDGPU/llvm.ceil.f16.ll
test/CodeGen/AMDGPU/llvm.cos.f16.ll
test/CodeGen/AMDGPU/llvm.exp2.f16.ll
test/CodeGen/AMDGPU/llvm.exp2.ll
test/CodeGen/AMDGPU/llvm.floor.f16.ll
test/CodeGen/AMDGPU/llvm.fma.f16.ll
test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
test/CodeGen/AMDGPU/llvm.log2.f16.ll
test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
test/CodeGen/AMDGPU/llvm.minnum.f16.ll
test/CodeGen/AMDGPU/llvm.rint.f16.ll
test/CodeGen/AMDGPU/llvm.sin.f16.ll
test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
test/CodeGen/AMDGPU/llvm.trunc.f16.ll
test/CodeGen/AMDGPU/select.f16.ll
test/CodeGen/AMDGPU/sitofp.f16.ll
test/CodeGen/AMDGPU/uitofp.f16.ll
test/CodeGen/AMDGPU/v_mac_f16.ll