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(parent: 6f3eb1a) | patch
target/riscv: Add csr support for svadu
authorWeiwei Li <liweiwei@iscas.ac.cn>
Fri, 24 Feb 2023 04:08:49 +0000 (12:08 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 2 Mar 2023 01:28:15 +0000 (17:28 -0800)
commit0d190bd3948402257b8ca218cd63ee8bbb78b76c
treefe4bae5b7fe7e9bfb8dcee36a58f8579b5920c1atree | snapshot
parent6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203commit | diff
target/riscv: Add csr support for svadu

Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
target/riscv/cpu.h diff | blob | history
target/riscv/cpu_bits.h diff | blob | history
target/riscv/csr.c diff | blob | history
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