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target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 8 Jul 2022 15:15:12 +0000 (20:45 +0530)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 11 Jul 2022 12:19:35 +0000 (13:19 +0100)
commit0d935760346b7ea07cbf5f63667151198012c922
treeb0997ab4334a9d8da88bc56f9e73f64911f0045ctree | snapshot
parent285b1d5fcef3ef352333f08bde669551054fbee4commit | diff
target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/sve.decode diff | blob | history
target/arm/translate-a64.h diff | blob | history
target/arm/translate-sve.c diff | blob | history
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