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author	Evan Cheng <evan.cheng@apple.com>
	Thu, 30 Sep 2010 01:08:25 +0000 (01:08 +0000)
committer	Evan Cheng <evan.cheng@apple.com>
	Thu, 30 Sep 2010 01:08:25 +0000 (01:08 +0000)
commit	0e55fd61ae9ab88cf76b30f7e69d168bd7be87d0
tree	bb48dbf4efcf1f8f1752090f8ff3242ac6829e60	tree \| snapshot
parent	9510a2538bcf5e3b42b9ee02ff527fd6681af0ad	commit \| diff

ARM instruction itinerary fixes:
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8

external/llvm

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lib/Target/ARM/ARMInstrInfo.td		diff \| blob \| history
lib/Target/ARM/ARMInstrThumb.td		diff \| blob \| history
lib/Target/ARM/ARMInstrThumb2.td		diff \| blob \| history
lib/Target/ARM/ARMSchedule.td		diff \| blob \| history
lib/Target/ARM/ARMScheduleA8.td		diff \| blob \| history
lib/Target/ARM/ARMScheduleA9.td		diff \| blob \| history
lib/Target/ARM/ARMScheduleV6.td		diff \| blob \| history